Datasheet IS61SP6464-133PQ, IS61SP6464-117TQI, IS61SP6464-117TQ, IS61SP6464-117PQ, IS61SP6464-100TQI Datasheet (ISSI)
...
®
IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
FEATURES
• Fast access time:
– 133, 117, 100 MHz; 6 ns (83 MHz);
7 ns (75 MHz); 8 ns (66 MHz)
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or VCCQ to alter their power-up state
ISSI
APRIL 2001
DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 64 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
Q
pins. Subsequent burst addresses can be generated internally by the IS61SP6464 and controlled by the ADV (burst
address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GND
pin selects LINEAR Burst. A VCCQ (or no connect) on MODE
pin selects INTERLEAVED Burst.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Q, on MODE
1
IS61SP6464
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
CLK
BINARY
COUNTER
CE
CLR
Q0
Q1
MODE
®
ISSI
A0
A1
A0'
A1'
64K x 64
MEMORY
ARRAY
A15-A0
GW
BWE
BW8
BW1
CE
CE2
CE2
CE3
CE3
16
D
ADDRESS
REGISTER
CE
D
DQ57-DQ64
BYTE WRITE
REGISTERS
D
BYTE WRITE
REGISTERS
D
REGISTER
CE
Q
CLK
Q
CLK
Q
DQ8-DQ1
CLK
Q
ENABLE
CLK
14 16
8
REGISTERS
64
INPUT
CLK
64
OUTPUT
REGISTERS
CLK
OE
64
DATA[64:1]
D
REGISTER
OE
2
Q
ENABLE
DELAY
CLK
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP6464
PIN CONFIGURATION
128-Pin TQFP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCQ
1
2
33
3
34
4
35
5
36
6
37
7
38
8
39
9
40
10
41
11
42
12
43
13
14
15
44
16
45
17
46
18
47
19
48
20
49
21
50
22
51
23
52
24
53
25
26
27
54
28
55
29
56
30
57
31
58
32
59
33
60
34
61
35
62
36
63
37
64
38
GNDQ
VCCQ
GNDQ
VCCQ
GNDQ
VCCQ
CE3
CE2
CE3
CE2
GND
VCCCEBW8
BW7
BW6
BW5OECLK
BWEGWBW4
BW3
GND
VCC
BW2
BW1
ADSC
ADSP
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
39404142434445464748495051525354555657585960616263
ADV
104
GNDQ
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
VCCQ
32
I/O
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
I/O
24
I/O
23
I/O
22
GNDQ
VCCQ
21
I/O
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VCCQ
11
I/O
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
GNDQ
®
ISSI
A9
A15
GNDQNCMODE
A14
A13
VCC
GND
A12
A11
A10
A8NCA7A6A5A4A3
PIN DESCRIPTIONS
A0-A15 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW8 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE, CE2, CE2, Synchronous Chip Enable
CE3, CE3
OE Output Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
GND
VCCQ
ZZ
A2A1A0
VCC
I/O1-I/O64 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V
NC No Connect
GNDQ Isolated Output Buffer Ground
3
IS61SP6464
ISSI
TRUTH TABLE
ADDRESS
OPERATION USED CE3 CE2 CE3 CE2 CE ADSP ADSC ADV WRITE OE CLK I/O
Deselected, Power-down None X X X X H X L X X X L-H High-Z
Deselected, Power-down None L X X X L L XXXXL-HHigh-Z
Deselected, Power-down None X L X X L L XXXXL-HHigh-Z
Deselected, Power-down None X X H X L L XXXXL-HHigh-Z
Deselected, Power-down None X X X H L L XXXXL-HHigh-Z
Deselected, Power-down None L X X X L H L X X X L-H High-Z
Deselected, Power-down None X L X X L H L X X X L-H High-Z
Deselected, Power-down None X X H X L H L X X X L-H High-Z
Deselected, Power-down None X X X H L H L X X X L-H High-Z
Read Cycle, Begin Burst External H H L L L L X X X L L-H Dout
Read Cycle, Begin Burst External H H L L L L X X X H L-H High-Z
Write Cycle, Begin Burst External H H L L L H L X L X L-H Din
Read Cycle, Begin Burst External H H L L L H L X H L L-H Dout
Read Cycle, Begin Burst External H H L L L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X X X H H L H L L-H Dout
Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z
Read Cycle, Continue Burst Next X X X X H X H L H L L-H Dout
Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din
Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din
Read Cycle, Suspend Burst Current X X X X X HHHHLL-HDout
Read Cycle, Suspend Burst Current X X X X X HHHHHL-HHigh-Z
Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout
Read Cycle, Suspend Burst Current X X X X H X HHHHL-HHigh-Z
Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din
Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61SP6464
ISSI
ASYNCHRONOUS TRUTH TABLE
Operation ZZ OE I/O STATUS
Pipelined Read L L Dout
Pipelined Read L H High-Z
Write L L High-Z
Write L H Din
Deselect L X High-Z
Sleep H X High-Z
WRITE TRUTH TABLE
Operation GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1
Read HHXX XXXXXX
Read H LHH HHHHHH
Write all bytes H L L L L L L L L L
Write all bytes L X X X X X X X X X
Write Byte 1 H L H H H H H H H L
Write Byte 2 H L H H H H H H L H
Write Byte 3 H L H H H H H L H H
Write Byte 4 H L H H H H L H H H
Write Byte 5 H L H H H L H H H H
Write Byte 6 H L H H L H H H H H
Write Byte 7 H L H L H H H H H H
Write Byte 8 H L L H H H H H H H
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5
IS61SP6464
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
0,1A1’, A0’ = 1,1
1,0
®
ISSI
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.0 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
(1)
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP6464
®
ISSI
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 8 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND - VIN - VCCQ
ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. –22µA
CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF
COUT Input/Output Capacitance VOUT = 0V 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
(1,2)
A = 25°C, f = 1 MHz, Vcc = 3.3V.
(1)
(Over Operating Range)
(2)
Com. –22µA
Ind. –10 10
Ind. –10 10
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
O
= 50Ω
Z
Output
30 pF
50Ω
Buffer
1.5V
Figure 1
3.3V
OUTPUT
5 pF
Including
jig and
scope
Figure 2
317 Ω
351 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
7
IS61SP6464
ISSI
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-133 -117 -100 -6 -7 -8
Symbol Parameter Test Conditions
ICC AC Operating Device Selected, Com. 280 270 250 200 170 150 mA
Supply Current All Inputs = VIL or VIH Ind. — 290 270 220 190 170
OE = VIH,
Cycle Time • tKC min.
ISB1 Standby Current Device Deselected, Com. 70 70 70 70 70 70 mA
TTL Inputs VCC = Max., Ind. — 80 80 80 80 80
All Inputs = VIH or VIL
CLK Cycle Time • tKC min.
ISB2 Standby Current Device Deselected, Com. 20 20 20 20 20 20 mA
CMOS Inputs VCC = Max., Ind. — 30 30 30 30 30
VIN = VCC • 0.2V, or VIN - 0.2V
CLK Cycle Time • tKC min.
IZZ Power-Down Mode ZZ = VCCQ, CLK Running Com. 20 20 20 20 20 20 mA
Current All Inputs - GND + 0.2V Ind. — 30 30 30 30 30
or • VCC – 0.2V
Notes:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or • Vcc – 0.2V.
Max. Max. Max. Max. Max. Max. Uni
®
t
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61SP6464
ISSI
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5ns
(1)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 1.5 — 1.5 — 2.5 — ns
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Clock High to Output High-Z 2 5 2 5 2 5 ns
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Output Disable to Output High-Z —— —— 25ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
9
®
IS61SP6464
ISSI
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8ns
(1)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 2.5 — 3 — 3 — ns
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Clock High to Output High-Z 2 5 2 5 2 6 ns
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Output Disable to Output High-Z 2 5 2 5 2 6 ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP6464
READ CYCLE TIMING
CLK
t
SS
ADSP
t
SH
t
KH
t
KC
®
ISSI
t
KL
ADSP is blocked by CE inactive
ADSC
ADV
A15-A0
GW
BWE
BW8-BW1
CE
CE2, CE3
t
AS
t
AH
RD1 RD2
t
WS
t
WS
t
CES
t
CES
t
CEH
t
CEH
t
SS
t
WH
t
WH
ADSC initiate read
t
AVS
t
SH
t
AVH
Suspend Burst
RD3
CE Masks ADSP
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
Unselected with CE2, CE3
t
CES
t
CEH
CE2, CE3
t
t
OEQ
OEHZ
OE
t
OEQX
1a
DATA
OUT
DATA
IN
High-Z
High-Z
t
t
KQLZ
OELZ
t
KQ
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
2a 2b
Burst Read
2c 2d 3a
Pipelined Read
t
KQX
t
KQHZ
Unselected
11
IS61SP6464
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns
®
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Single Write
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW8-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61SP6464
WRITE CYCLE TIMING
®
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
13
®
IS61SP6464
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4. — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5ns
(1)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 1.5 — 1.5 — 2.5 — ns
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Clock High to Output High-Z 1.5 7.5 1.5 8.5 2 5 ns
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Output Disable to Output High-Z —— —— 25ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61SP6464
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8ns
(1)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 2.5 — 3 — 3 — ns
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Clock High to Output High-Z 2 5 2 5 2 6 ns
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(1,2)
Output Disable to Output High-Z 2 5 2 5 2 6 ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
15
IS61SP6464
READ/WRITE CYCLE TIMING
t
KC
CLK
t
t
SH
t
AH
KH
t
SS
ADSP
ADSC
ADV
t
t
SS
AS
t
KL
t
®
ISSI
ADSP is blocked by CE inactive
SH
A15-A0
GW
BWE
BW8-BW1
CE
CE2, CE3
CE2, CE3
OE
RD1 WR1
t
WS
t
WS
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
OEQ
t
WH
t
WH
RD2 RD3
t
WS
t
WH
WR1
CE Masks ADSP
CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC
Unselected with CE2, CE3
t
OEHZ
16
DATA
OUT
DATA
IN
High-Z
High-Z
t
OELZ
t
KQLZ
t
Single Read
KQ
t
OEQX
1a
t
KQX
t
KQHZ
t
DS
Single Write
1a
t
DH
t
KQX
2a 2b 2c 2d
t
KQHZ
Burst Read
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61SP6464
ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5ns
(3)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 4 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 0 ———2.5 — ns
(3,4)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(3,4)
Clock High to Output High-Z 1.5 7.5 1.5 8.5 2 5 ns
(3)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(3,4)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(3,4)
Output Disable to Output High-Z —— —— 25ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby
tZZREC ZZ Recovery
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
(1)
(2)
2 — 2 — 2 — cyc
2 — 2 — 2 — cyc
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
17
®
IS61SP6464
ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8ns
(3)
tKQX
tKQLZ
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
tOELZ
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 2.5 — 3 — 3 — ns
(3,4)
Clock High to Output Low-Z 0 — 0 — 0 — ns
(3,4)
Clock High to Output High-Z 2 5 2 5 2 6 ns
(3)
Output Disable to Output Invalid 0 — 0 — 0 — ns
(3,4)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
(3,4)
Output Disable to Output High-Z 2 5 2 5 2 6 ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby
tZZREC ZZ Recovery
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
(1)
(2)
2 — 2 — 2 — cyc
2 — 2 — 2 — cyc
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
ZZ
t
ZZS
t
ZZREC
IS61SP6464
SNOOZE AND RECOVERY CYCLE TIMING
®
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
19
IS61SP6464
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
133 IS61SP6464-133TQ TQFP
IS61SP6464-133PQ PQFP
117 IS61SP6464-117TQ TQFP
IS61SP6464-117PQ PQFP
100 IS61SP6464-100TQ TQFP
IS61SP6464-100PQ PQFP
83 IS61SP6464-6TQ TQFP
IS61SP6464-6PQ PQFP
75 IS61SP6464-7TQ TQFP
IS61SP6464-7PQ PQFP
66 IS61SP6464-8TQ TQFP
IS61SP6464-8PQ PQFP
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
133 IS61SP6464-133TQI TQFP
IS61SP6464-133PQI PQFP
117 IS61SP6464-117TQI TQFP
IS61SP6464-117PQI PQFP
100 IS61SP6464-100TQI TQFP
IS61SP6464-100PQI PQFP
83 IS61SP6464-6TQI TQFP
IS61SP6464-6PQI PQFP
75 IS61SP6464-7TQI TQFP
IS61SP6464-7PQI PQFP
66 IS61SP6464-8TQI TQFP
IS61SP6464-8PQI PQFP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
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