Datasheet IS61SP25618-5TQI, IS61SP25618-5B, IS61SP25618-166TQ, IS61SP25618-166B, IS61SP25618-150TQI Datasheet (ISSI)
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IS61SP25616
IS61SP25618 ISSI
256K x 16, 256K x 18 SYNCHRONOUS
®
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, -5% power supply
• Power-down snooze mode
APRIL 2001
DESCRIPTION
The ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with ISSI's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol Parameter -166 -150 -133 -5 Units
tKQ Clock Access Time 3.5 3.8 4 5 ns
tKC Cycle Time 6 6.7 7.5 10 ns
Frequency 166 150 133 100 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
IS61SP25616
IS61SP25618 ISSI
BLOCK DIAGRAM
MODE
ADV
CLK
ADSC
ADSP
CLK2
BURST
COUNTER
CLR
2 18
256K x 16/256K x 18
MEMORY ARRAY
®
A2-A17
A1
A0
BWE
BW1
BW2
GW
ADDRESS
REGISTER
BW1
BYTE WRITE
REGISTER
BW2
BYTE WRITE
REGISTER
CLK2
2
18
CLK
16
CLK
16 or 18
2
DATA
INPUT
REGISTER
16 or 18
DATA
OUTPUT
REGISTER
CE1
CE2
CE2
OE
ENABLE
REGISTER
ENABLE
REGISTER
DQ1 - DQ16
or
DQ1 - DQ18
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
®
1 2 3 4 5 6 7
A
VCCQ
B
NC
C
NC
D
DQ9
E
NC
F
VCCQ
G
NC
H
DQ12
J
VCCQ
K
NC
L
DQ14
M
VCCQ
N
DQ16
P
NC
R
NC
T
NC
U
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
NC
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
NC
A14
NC
A16
CE2
A15
NC
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
NC
NC
GND
VCCQ
NC
NC
NC
BW2
BW1
A6
A7CECE2NCNC
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
A5A4A3A2A1
MODE
CE2
A0
NC
NC
VCC
GND
GND
VCC
CLK
NC
GW
NC
BWEOEADSC
46 47 48 49 50
A10
A11
A12
ADSP
ADV
A13
A14
A8
A15
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A16
A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 16
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
3
IS61SP25616
IS61SP25618 ISSI
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
®
1 2 3 4 5 6 7
A
VCCQ
B
C
D
DQ9
E
F
VCCQ
G
H
DQ12
J
VCCQ
K
L
DQ14
M
VCCQ
N
DQ16
P
R
T
U
VCCQ
NC
NC
NC
NC
NC
NC
NC
NC
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
BW2
BW1
A6
A7CECE2NCNC
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
A5A4A3A2A1
MODE
CE2
A0
NC
NC
VCC
GND
GND
VCC
CLK
NC
GW
NC
BWEOEADSC
46 47 48 49 50
A10
A11
A12
ADSP
ADV
A13
A14
A8
A15
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A16
A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
4
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
DQP1-DQP2
Parity Data I/O DQP1 is parity for DQ1-8;
DQP2 is parity for DQ9-16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
TRUTH TABLE
Address
Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXQ
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
®
PARTIAL TRUTH TABLE
Function GW BWE BW1 BW2
Read H H X X
Read H L H H
Write Byte 1 H L L H
Write All Bytes H L L L
Write All Bytes L X X X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5
IS61SP25616
IS61SP25618 ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
®
0,1A1', A0' = 1,1
1,0
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
(1)
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V, +10%, –5%
Industrial –40°C to +85°C 3.3V, +10%, –5%
®
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VCCQ
(2)
Com. –22µA
Ind. –55
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. –22µA
Ind. –55
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166 -
Symbol Parameter Test Conditions
Max. Max. Max Max. Uni
ICC AC Operating Device Selected, Com. 210 190 170 160 mA
Supply Current All Inputs = VIL or VIH Ind. — 200 180 170 mA
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 60 60 60 60 mA
VCC = Max., Ind. — 70 70 70 mA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
IZZ Power-down Mode ZZ = V CC Com. 15 15 15 15 mA
Current Clock Running Ind. — 20 20 20 mA
All Inputs ≤ GND + 0.2V
or ≥ Vcc – 0.2V
150
-
133
-5
t
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V
2. The MODE pin could be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V
or ≥ Vcc – 0.2V.
CC.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
7
IS61SP25616
IS61SP25618 ISSI
®
CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
(1,2)
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
O
= 50Ω
Z
Output
30 pF
50Ω
Buffer
1.5V
Figure 1 Figure 2
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
3.3V
OUTPUT
5 pF
Including
jig and
scope
317 Ω
351 Ω
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
(3)
fMAX
(3)
tKC
tKH Clock High Time 2.4 — 2.6 — 2.8 — 3 — ns
(3)
tKL
(3)
tKQ
(1)
tKQX
(1,2)
tKQLZ
(1,2)
tKQHZ
(3)
tOEQ
(1)
tOEQX
(1,2)
tOELZ
(1,2)
tOEHZ
(3)
tAS
(3)
tSS
(3)
tWS
(3)
tCES
(3)
tAVS
(3)
tAH
(3)
tSH
(3)
tWH
(3)
tCEH
(3)
tAVH
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
Clock Frequency — 166 — 150 — 133 — 100 MHz
Cycle Time 6 — 6.7 — 7.5 — 10 — ns
Clock Low Time 2.4 — 2.6 — 2.8 — 3 — ns
Clock Access Time — 3.5 — 3.8 — 4 — 5ns
Clock High to Output Invalid 3 — 3 — 3 — 3 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns
Output Enable to Output Valid — 3.5 — 3.5 — 3.8 — 5ns
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 5 ns
Address Setup Time 2 — 2 — 2 — 2 — ns
Address Status Setup Time 2 — 2 — 2 — 2 — ns
Write Setup Time 2 — 2 — 2 — 2 — ns
Chip Enable Setup Time 2 — 2 — 2 — 2 — ns
Address Advance Setup Time 2 — 2 — 2 — 2 — ns
Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
9
IS61SP25616
IS61SP25618 ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
t
KL
t
AVS
t
SH
t
AVH
ADSP is blocked by CE inactive
ADSC initiate read
Suspend Burst
ADSP
ADSC
ADV
t
t
SS
AS
t
SH
t
AH
t
KH
t
SS
®
A17-A0
GW
BWE
BW2-BW1
CE
CE2
CE2
OE
RD1 RD2
t
WS
t
WS
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
OEQ
t
WH
t
WH
RD3
CE Masks ADSP
CE2 and CE2 only sampled with ADSP or ADSC
t
OEHZ
Unselected with CE2
10
DATA
OUT
DATA
IN
High-Z
High-Z
t
OELZ
t
KQLZ
t
Single Read
KQ
t
OEQX
1a
2a 2b
2c 2d 3a
Pipelined Read
Burst Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
t
KQX
t
KQHZ
Unselected
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
(1)
tKC
tKH
(1)
tKL
tAS
tSS
tWS
tDS
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Cycle Time 6 — 6.7 — 7.5 — 10 — ns
Clock High Time 2.4 — 2.6 — 2.8 — 4 — ns
Clock Low Time 2.4 — 2.6 — 2.8 — 4 — ns
Address Setup Time 2 — 2 — 2 — 2 — ns
Address Status Setup Time 2 — 2 — 2 — 2 — ns
Write Setup Time 2 — 2 — 2 — 2 — ns
Data In Setup Time 2 — 2 — 2 — 2 — ns
Chip Enable Setup Time 2 — 2 — 2 — 2 — ns
Address Advance Setup Time 2 — 2 — 2 — 2 — ns
Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
®
Note:
1. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
11
IS61SP25616
IS61SP25618 ISSI
WRITE CYCLE TIMING
t
KC
CLK
t
KL
t
AVS
ADSP is blocked by CE inactive
ADSC initiate Write
t
AVH
ADSP
ADSC
ADV
t
t
SS
AS
t
KH
t
SH
ADV must be inactive for ADSP Write
t
AH
®
A17-A0
GW
BWE
BW2-BW1
CE
CE2
CE2
OE
WR1 WR2
t
WS
t
WS
t
WS
WR1 WR2
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
WH
t
WH
t
WH
WR3
t
WS
t
WH
WR3
CE Masks ADSP
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
12
DATA
OUT
DATA
IN
High-Z
t
DS
High-Z
Single Write
1a
t
DH
BW4-BW1 only are applied to first cycle of WR2
2c 2d2b2a
Burst Write
Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
3a
Unselected
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
(3)
tKC
(3)
tKH
(3)
tKL
(3)
tKQ
(1)
tKQX
tKQLZ
tKQHZ
(3)
tOEQ
tOEQX
tOELZ
tOEHZ
(3)
tAS
(3)
tSS
(3)
tCES
(3)
tAH
(3)
tSH
(3)
tCEH
tZZS ZZ Standby 2 — 2 — 2 — 2 — cyc
tZZREC ZZ Recovery 2 — 2 — 2 — 2 — cyc
Cycle Time 6 — 6.7 — 7.5 — 10 — ns
Clock High Time 2.4 — 2.6 — 2.8 — 4 — ns
Clock Low Time 2.4 — 2.6 — 2.8 — 4 — ns
Clock Access Time — 3.5 — 3.8 — 4 — 5ns
Clock High to Output Invalid 1.5 — 1.5 — 1.5 — 2.5 — ns
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns
Output Enable to Output Valid — 3.5 — 3.5 — 3.9 — 5ns
(1)
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
(1,2)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
(1,2)
Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 5 ns
Address Setup Time 2 — 2 — 2 — 2 — ns
Address Status Setup Time 2 — 2 — 2 — 2 — ns
Chip Enable Setup Time 2 — 2 — 2 — 2 — ns
Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
®
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
13
IS61SP25616
IS61SP25618 ISSI
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
t
KL
ADSP
ADSC
ADV
t
t
SS
AS
t
SH
t
AH
t
KH
®
A17-A0
GW
BWE
BW2-BW1
CE
CE2
CE2
OE
t
CES
t
CES
t
CES
RD1
t
CEH
t
CEH
t
CEH
t
OEQ
t
OEHZ
RD2
14
DATA
OUT
DATA
IN
ZZ
High-Z
High-Z
t
OELZ
t
KQLZ
Single Read
t
KQ
t
OEQX
1a
t
KQX
t
KQHZ
t
ZZS
t
ZZREC
Snooze with Data Retention
Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61SP25616
IS61SP25618 ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61SP25616-166TQ TQFP
IS61SP25616-166B PBGA
150 MHz IS61SP25616-150TQ TQFP
IS61SP25616-150B PBGA
133 MHz IS61SP25616-133TQ TQFP
IS61SP25616-133B PBGA
5 ns IS61SP25616-5TQ TQFP
IS61SP25616-5B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SP25616-150TQI TQFP
133 MHz IS61SP25616-133TQI TQFP
5 ns IS61SP25616-5TQI TQFP
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61SP25618-166TQ TQFP
IS61SP25618-166B PBGA
150 MHz IS61SP25618-150TQ TQFP
IS61SP25618-150B PBGA
133 MHz IS61SP25618-133TQ TQFP
IS61SP25618-133B PBGA
5 ns IS61SP25618-5TQ TQFP
IS61SP25618-5B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SP25618-150TQI TQFP
133 MHz IS61SP25618-133TQI TQFP
5 ns IS61SP25618-5TQI TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
15
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