Datasheet IS61SF6436-9PQ, IS61SF6436-8.5TQ, IS61SF6436-8.5PQ, IS61SF6436-10PQI, IS61SF6436-10PQ Datasheet (ISSI)
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IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
• Fast access times: 8.5 ns, 9 ns, 10 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
Q
or VCCQ to alter their power-up state
DESCRIPTION
The ISSI IS61SF6436 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 36 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and
DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4
controls DQP4 and DQ25-DQ32, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally by the IS61SF6436 and controlled by the ADV (burst
address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
Q, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
64K x 36 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
APRIL 2001
IS61SF6436 ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
BLOCK DIAGRAM
16
BINARY
COUNTER
A15-A0
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
14 16
ADDRESS
REGISTER
CE
D
CLK
Q
DQP4
DQ31-DQ24
BYTE WRITE
REGISTERS
D
CLK
Q
DQP3
DQ23-DQ16
BYTE WRITE
REGISTERS
D
CLK
Q
DQP2
DQ15-DQ8
BYTE WRITE
REGISTERS
D
CLK
Q
DQP1
DQ8-DQ0
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW4
CE
CE2
CE2
BW2
BW3
64K x 36
MEMORY
ARRAY
36
INPUT
REGISTERS
CLK
36
OE
4
36
OE
DATA[35.0]
FT
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
04/17/01
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
PIN DESCRIPTIONS
A0-A15 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW4 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ32 Data Input/Output
DQP1-DQP4 Parity Inputs/Outputs
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V
GNDQ Isolated Output Buffer Ground
DQP2
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
DQP1
A6A7CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLKGWBWEOEADSC
ADSP
ADVA8A9
DQP3
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
GNDQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
DQP4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5A4A3A2A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
NC
46 47 48 49 50
IS61SF6436 ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
TRUTH TABLE
ADDRESS
OPERATION USED CE CE2 CE2 ADSP ADSC A DV WRITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X L L XXXXHigh-Z
Deselected, Power-down None L H X L XXXXHigh-Z
Deselected, Power-down None L X L H L X X X High-Z
Deselected, Power-down None L H X H L X X X High-Z
Read Cycle, Begin Burst External L L H L X X X L Q
Read Cycle, Begin Burst External L L H L X X X H High-Z
Write Cycle, Begin Burst External L L H H L X L X D
Read Cycle, Begin Burst External L L H H L X H L Q
Read Cycle, Begin Burst External L L H H L X H H High-Z
Read Cycle, Continue Burst Next X X X H H L H L Q
Read Cycle, Continue Burst Next X X X H H L H H High-Z
Read Cycle, Continue Burst Next H X X X H L H L Q
Read Cycle, Continue Burst Next H X X X H L H H High-Z
Write Cycle, Continue Burst Next X X X H H L L X D
Write Cycle, Continue Burst Next H X X X H L L X D
Read Cycle, Suspend Burst Current X X X HHHHLQ
Read Cycle, Suspend Burst Current X X X HHHHHHigh-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X HHHHHigh-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
FUNCTION GW B W E BW1 BW2 BW3 BW4
READ H H X X X X
READ H L H H H H
WRITE Byte 1 H L L H H H
WRITE All Bytes H LLLLL
WRITE All Bytes L XXXXX
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
04/17/01
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
1,0
0,1A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.8 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
IS61SF6436 ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
I
LI Input Leakage Current GND - VIN - VCCQ
(2)
Com. –55µA
Ind. –10 10
ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. –55µA
Ind. –10 10
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-8.5 -9-10
Symbol Parameter Test Conditions
Typ. Max. Typ. Max. Typ. Max. Uni
t
ICC AC Operating Device Selected, Com. 190 220 180 210 170 200 mA
Supply Current All Inputs = VIL or VIH Ind. —— —— 180 210 mA
OE = VIH,
Cycle Time • tKC min.
ISB Standby Current Device Deselected, Com. 45 70 45 70 45 70 mA
VCC = Max., Ind. —— —— 50 75 mA
All Inputs = VIH or VIL
CLK Cycle Time • tKC min.
IZZ Power-Down Mode ZZ = VCCQ, CLK Running Com. 1 10 1 10 1 10 mA
Current All Inputs - GND + 0.2V Ind. —— —— 220 mA
or • VCC – 0.2V
Note:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
V
CCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or • Vcc – 0.2V.
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
04/17/01
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Output
Buffer
Z
O
= 50Ω
1.5V
50Ω
30 pF
Figure 1
IS61SF6436 ISSI
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-8.5 -9 -10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4.5 — 5 — ns
tKL Clock Low Time 4 — 4.5 — 5 — ns
tKQ Clock Access Time — 8.5 — 9 — 10 ns
tKQX
(1)
Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z 2 5 2 5 2 5 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/17/01
READ CYCLE TIMING
Single Read
Flow-through
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1 RD2
1a
2c 2d 3a
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
KQLZ
t
KQ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
2a 2b
IS61SF6436 ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-8.5 -9 -10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4.5 — 5 — ns
tKL Clock Low Time 4 — 4.5 — 5 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
04/17/01
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61SF6436 ISSI
®
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-8.5 -9 -10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4.5 — 5 — ns
tKL Clock Low Time 4 — 4.5 — 5 — ns
tKQ Clock Access Time — 8.5 — 9 — 10 ns
tKQX
(1)
Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ
(1,2)
Clock High to Output High-Z 2 5 2 5 2 6 ns
tOEQX
(1)
Output Disable to Output Invalid 0 — 0 — 0 — ns
tOEHZ
(1,2)
Output Disable to Output High-Z 2 5 2 5 2 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
04/17/01
READ/WRITE CYCLE TIMING
Single Read
Flow-through
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQX
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
t
KQLZ
IS61SF6436 ISSI
®
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-8.5 -9 -10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4.5 — 5 — ns
tKL Clock Low Time 4 — 4.5 — 5 — ns
tKQ Clock Access Time — 8.5 — 9 — 10 ns
tKQX
(3)
Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ
(3,4)
Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ
(3,4)
Clock High to Output High-Z 2 5 2 5 2 6 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5ns
tOEQX
(3)
Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ
(3,4)
Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ
(3,4)
Output Disable to Output High-Z 2 5 2 5 2 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby
(1)
2 — 2 — 2 — cyc
tZZREC ZZ Recovery
(2)
2 — 2 — 2 — cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
IS61SF6436 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
ZZ
t
ZZS
t
ZZREC
IS61SF6436 ISSI
®
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part Number Package
8.5 IS61SF6436-8.5TQ TQFP
8.5 IS61SF6436-8.5PQ PQFP
9 IS61SF6436-9TQ TQFP
9 IS61SF6436-9PQ PQFP
10 IS61SF6436-10TQ TQFP
10 IS61SF6436-10PQ PQFP
Industrial Range: –40°C to +85°C
Speed (ns) Order Part Number Package
10 IS61SF6436-10TQI TQFP
10 IS61SF6436-10PQI PQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
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