Datasheet IS61S6432-8PQ, IS61S6432-7TQI, IS61S6432-7PQI, IS61S6432-7PQ, IS61S6432-8TQI Datasheet (ISSI)
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IS61S6432 ISSI
64K x 32 SYNCHRONOUS
®
PIPELINE STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
JUNE 2001
DESCRIPTION
The
ISSI
IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edgetriggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the powerdown state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.
Q, on MODE pin selects
ISSI
's advanced
FAST ACCESS TIME
Symbol Parameter -200
tKQ CLK Access Time 45555678ns
tKC Cycle Time 5 6 7.5 8.5 10 12 13 15 ns
— Frequency 200 166 133 117 100 83 75 66 MHz
Note:
1. ADVANCE INFORMATION ONLY.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
(1)
-166 -133 -117 -5 -6 -7 -8 Unit
1
IS61S6432 ISSI
BLOCK DIAGRAM
MODE
CLK
ADV
ADSC
ADSP
CLK
BINARY
COUNTER
CE
CLR
Q0
Q1
A0
A1
A0'
A1'
64K x 32
MEMORY
ARRAY
®
A15-A0
GW
BWE
BW4
BW3
BW2
BW1
16
D
Q
14 16
ADDRESS
REGISTER
CE
CLK
D
Q
32
32
DQ32-DQ25
BYTE WRITE
REGISTERS
CLK
D
Q
DQ24-DQ17
BYTE WRITE
REGISTERS
CLK
D
Q
DQ16-DQ9
BYTE WRITE
REGISTERS
CLK
D
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
PB
CE1
CE2
CE3
OE
D
ENABLE
REGISTER
CE
CLK
D
ENABLE
DELAY
REGISTER
CLK
4
Q
Q
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
32
DATA[32:1]
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
A6A7CE1
CE2
BW4
BW3
BW2
BW1
CE3
VCC
GND
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
CLKGWBWEOEADSC
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
ADSP
ADVA8A9
46 47 48 49 50
80
NC
79
DQ16
78
DQ15
77
VCCQ
76
GNDQ
75
DQ14
74
DQ13
73
DQ12
72
DQ11
71
GNDQ
70
VCCQ
69
DQ10
68
DQ9
67
GND
66
NC
65
VCC
64
ZZ
63
DQ8
62
DQ7
61
VCCQ
60
GNDQ
59
DQ6
58
DQ5
57
DQ4
56
DQ3
55
GNDQ
54
VCCQ
53
DQ2
52
DQ1
51
NC
®
A5A4A3A2A1
MODE
A0
NC
NC
GND
VCC
NC
NC
A10
PIN DESCRIPTIONS
A0-A15 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW4 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE1, CE2, CE3 Synchronous Chip Enable
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
A11
A12
A13
NC
A14
A15
OE Output Enable
DQ1-DQ32 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply: +3.3V
GNDQ Isolated Output Buffer Ground
NC No Connect
3
®
IS61S6432 ISSI
TRUTH TABLE
Address
Operation Used CE1 CE2 CE3 ADSP ADSC ADV WRITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X H L X X X High-Z
Deselected, Power-down None L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst External L H L L X X X H High-Z
Write Cycle, Begin Burst External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst External L H L H L X H H High-Z
Read Cycle, Continue Burst Next X X X H H L H L Q
Read Cycle, Continue Burst Next X X X H H L H H High-Z
Read Cycle, Continue Burst Next H X X X H L H L Q
Read Cycle, Continue Burst Next H X X X H L H H High-Z
Write Cycle, Continue Burst Next X X X H H L L X D
Write Cycle, Continue Burst Next H X X X H L L X D
Read Cycle, Suspend Burst Current X X X HHHHLQ
Read Cycle, Suspend Burst Current X X X HHHHHHigh-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X HHHHHigh-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function GW BWE BW1 BW2 BW3 BW4
READ H H X X X X
READ H X H H H H
WRITE Byte 1 H L L H H H
WRITE All Bytes X LLLLL
WRITE All Bytes L XXXXX
PB
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
0,1A1', A0' = 1,1
®
1,0
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.8 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for for Address and Control Inputs –0.5 to 5.5 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
(1,2,3)
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%
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Rev.B
06/28/01
5
IS61S6432 ISSI
®
DC ELECTRICAL CHARACTERISTICS
(1,2)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND - VIN - VCCQ
(2)
Com. –55µA
Ind. –10 10
ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. –55µA
Ind. –10 10
Notes:
1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,
tied to GND,or tied to V
2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied
to - GND + 0.2V or • Vcc – 0.2V.
CCQ.
POWER SUPPLY CHARACTERISTICS (Operating Range)
(1)
-200
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
-166 -133 -117
ICC AC Operating Device Selected, Com. — 400 — 215 — 205 — 195 mA
Supply Current All Inputs = VIL or VIH Ind. —— —— —— —205
OE = VIH, Cycle Time • tKC min.
ISB Standby Current Device Deselected, Com. — 100 — 70 — 60 — 50 mA
VCC = Max., Ind. —— —— —— —60
CLK Cycle Time • tKC min.
IZZ Power-Down ZZ = VCCQ, CLK Running Com. — 5 — 5 — 5 — 5mA
Mode Current All Inputs - GND + 0.2V Ind. —— —— —— —10
or • VCC – 0.2V
Note:
1. ADVANCE INFORMATION ONLY.
-5 -6 -7 -8
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC AC Operating Device Selected, Com. — 175 — 165 — 150 — 140 mA
Supply Current All Inputs = VIL or VIH Ind. — 185 — 175 — 160 — 150
OE = VIH, Cycle Time • tKC min.
ISB Standby Current Device Deselected, Com. — 25 — 25 — 25 — 25 mA
VCC = Max., Ind. — 35 — 35 — 35 — 35
CLK Cycle Time • tKC min.
IZZ Power-Down ZZ = VCCQ, CLK Running Com. — 5 — 5 — 5 — 5mA
Mode Current All Inputs - GND + 0.2V Ind. — 10 — 10 — 10 — 10
or • VCC – 0.2V
PB
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
®
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Output
Buffer
O
= 50Ω
Z
Figure 1
30 pF
1.5V
50Ω
3.3V
OUTPUT
5 pF
Including
jig and
scope
Figure 2
317 Ω
351 Ω
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
7
IS61S6432 ISSI
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
(1)
-200
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max Unit
tKC Cycle Time 5 — 6 — 7.5 — 8.5 — ns
tKH Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns
tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns
tKQ Clock Access Time — 4 — 5 — 5 — 5ns
(2)
tKQX
tKQLZ
tKQHZ
(2,3)
(2,3)
Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns
tOEQ Output Enable to Output Valid — 3.5 — 5 — 5 — 5ns
(2)
tOEQX
tOELZ
tOEHZ
(2,3)
(2,3)
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 3 — 3 — 3 — 4ns
-166 -133 -117
®
tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(4)
tCFG
Notes:
1. ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.
Configuration Setup 25 — 25 — 30 — 35 — ns
PB
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
(Continued)
-5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max Unit
tKC Cycle Time 10 — 12 — 13 — 15 — ns
tKH Clock High Time 3.5 — 4 — 6 — 6 — ns
tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 5 — 6 — 7 — 8ns
(1)
tKQX
tKQLZ
tKQHZ
(1,2)
(1,2)
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1.5 6 1.5 6 2626 ns
tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6ns
(1)
tOEQX
tOELZ
tOEHZ
(1,2)
(1,2)
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 4 — 5 — 6 — 6ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(3)
tCFG
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.
Configuration Setup 35 — 45 — 66.7 — 80 — ns
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
9
IS61S6432 ISSI
READ CYCLE TIMING: PIPELINE
t
KC
CLK
t
KL
ADSP is blocked by CE1 inactive
ADSP
t
SS
t
SH
t
KH
®
ADSC
ADV
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
t
AS
t
AH
RD1 RD2
t
WS
t
WS
t
CES
t
CES
t
CEH
t
CEH
t
SS
t
WH
t
WH
ADSC initiate read
t
AVS
t
SH
t
AVH
Suspend Burst
RD3
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
DATA
PB
CE3
OE
OUT
DATA
IN
t
CES
High-Z
High-Z
t
CEH
t
OEQ
t
OELZ
t
KQLZ
t
Single Read
KQ
t
OEQX
1a
t
OEHZ
2a 2b
Burst Read
t
KQX
2c 2d 3a
t
KQHZ
Pipelined Read
Unselected
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
(1)
-200
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 5 — 6 — 7.5 — 8.5 — ns
tKH Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns
tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns
tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
-166 -133 -117
®
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(2)
tCFG
Configuration Setup 25
—
25 — 30 — 35 — ns
-5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 10 — 12 — 13 — 15 — ns
tKH Clock High Time 3.5 — 4 — 6 — 6 — ns
tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(2)
tCFG
Note:
1. ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.
Configuration Setup 35 — 45 — 52 — 60 — ns
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
11
IS61S6432 ISSI
WRITE CYCLE TIMING
t
KC
CLK
t
KL
t
AVS
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
AVH
ADSP
ADSC
ADV
t
t
SS
AS
t
KH
t
SH
ADV must be inactive for ADSP Write
t
AH
®
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
OE
WR1 WR2
t
WS
t
WS
t
WS
WR1 WR2
t
CES
t
CES
t
CES
t
CEH
t
CEH
t
CEH
t
WH
t
WH
t
WH
WR3
t
WS
t
WH
WR3
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
DATA
PB
OUT
DATA
IN
High-Z
t
High-Z
Single Write
DS
1a
t
DH
BW4-BW1 only are applied to first cycle of WR2
2c 2d2b2a
Burst Write
Write
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3a
Unselected
Rev.B
06/28/01
IS61S6432 ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
(1)
-200
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 5 — 6 — 7.5 — 8.5 — ns
tKH Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns
tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns
tKQ Clock Access Time — 4 — 5 — 5 — 5ns
(2)
tKQX
tKQLZ
tKQHZ
(2,3)
(2,3)
Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns
Clock High to Output Low-Z — 0 — 0 — 0 — ns
Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns
tOEQ Output Enable to Output Valid — 3.5 — 5 — 5 — 5ns
(2)
tOEQX
tOELZ
tOEHZ
(2,3)
(2,3)
Output Disable to Output Invalid 0
—
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 3 — 3 — 3 — 4ns
tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
-166 -133 -117
0 — 0 — 0 — ns
®
tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(4)
tCFG
Notes:
1. ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.
Configuration Setup 25
—
25 — 30 — 35 — ns
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
13
IS61S6432 ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
(Continued)
-5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 10 — 12 — 13 — 15 — ns
tKH Clock High Time 3.5 — 4 — 6 — 6 — ns
tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 5 — 6 — 7 — 8ns
(1)
tKQX
tKQLZ
tKQHZ
(1,2)
(1,2)
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1.5 6 1.5 6 2626 ns
tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6ns
(1)
tOEQX
tOELZ
tOEHZ
(1,2)
(1,2)
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 4 — 5 — 6 — 6ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
(3)
tCFG
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Configuration signal MODE is static and must not change during normal operation.
Configuration Setup 35 — 45 — 52 — 60 — ns
PB
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
Single Read
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE1 inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE3
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
IS61S6432 ISSI
READ/WRITE CYCLE TIMING: PIPELINE
®
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
15
IS61S6432 ISSI
®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(2)
-200
-166 -133 -117
(1)
(Over Operating Range)
Symbol Parameter Min. Max. Min. Max Min. Max. Min. Max. Unit
tKC Cycle Time 5 — 6 — 7.5 — 8.5 — ns
tKH Clock High Time 1.6 — 2.4 — 2.8 — 3 — ns
tKL Clock Low Time 1.6 — 2.4 — 2.8 — 3 — ns
tKQ Clock Access Time — 4 — 5 — 5 — 5ns
(3)
tKQX
tKQLZ
tKQHZ
(3,4)
(3,4)
Clock High to Output Invalid 1 — 1.5 — 1.5 — 1.5 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1 3.5 1.5 5 1.5 5 1.5 6 ns
tOEQ Output Enable to Output Valid — 3.5 — 5 — 5 — 5ns
(3)
tOEQX
tOELZ
tOEHZ
(3,4)
(3,4)
Output Disable to Output Invalid 0
—
0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 3 — 3 — 3 — 4ns
tAS Address Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 2 — 2.5 — 2.5 — 2.5 — ns
tSH Address Status Hold Time 2 — 2.5 — 2.5 — 2.5 — ns
tCEH Chip Enable Hold Time 2 — 2.5 — 2.5 — 2.5 — ns
(5)
tZZS
(6)
tZZREC
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. ADVANCE INFORMATION ONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
ZZ Standby — 82— 2 — 2 — cyc
ZZ Recovery 8 — 2 — 2 — 2 — cyc
PB
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
(Continued)
-5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 10 — 12 — 13 — 15 — ns
tKH Clock High Time 3.5 — 4 — 6 — 6 — ns
tKL Clock Low Time 3.5 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 5 — 6 — 7 — 8ns
(2)
tKQX
(2,3)
tKQLZ
(2,3)
tKQHZ
tOEQ Output Enable to Output Valid — 5 — 6 — 6 — 6ns
(2)
tOEQX
(2,3)
tOELZ
(2,3)
tOEHZ
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — ns
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — ns
Clock High to Output Low-Z 0 — 0 — 0 — 0 — ns
Clock High to Output High-Z 1.5 6 1.5 6 2626 ns
Output Disable to Output Invalid 0 — 0 — 0 — 0 — ns
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — ns
Output Disable to Output High-Z — 4 — 5 — 6 — 6ns
tAH Address Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tSH Address Status Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns
tCEH Chip Enable Hold Time 2.5 — 2.5 — 2.5 — 2.5 — ns
(4)
tZZS
(5)
tZZREC
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
5. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
ZZ Standby 2 — 2 — 2 — 2 — cyc
ZZ Recovery 2 — 2 — 2 — 2 — cyc
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
17
IS61S6432 ISSI
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
t
KL
ADSP
ADSC
ADV
t
t
SS
AS
t
SH
t
AH
t
KH
®
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
OE
t
CES
t
CES
t
CES
RD1
t
CEH
t
CEH
t
CEH
t
OEQ
t
OEHZ
RD2
PB
DATA
OUT
DATA
IN
ZZ
High-Z
High-Z
t
OELZ
t
KQLZ
Single Read
t
KQ
t
OEQX
1a
t
KQX
t
KQHZ
t
ZZS
t
ZZREC
Snooze with Data Retention
Read
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
IS61S6432 ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency (MHz) Order Part Number Package
200 IS61S6432-200TQ TQFP
IS61S6432-200PQ PQFP
166 IS61S6432-166TQ TQFP
IS61S6432-166PQ PQFP
133 IS61S6432-133TQ TQFP
IS61S6432-133PQ PQFP
117 IS61S6432-117TQ TQFP
IS61S6432-117PQ PQFP
100 IS61S6432-5TQ TQFP
IS61S6432-5PQ PQFP
83 IS61S6432-6TQ TQFP
IS61S6432-6PQ PQFP
75 IS61S6432-7TQ TQFP
IS61S6432-7PQ PQFP
66 IS61S6432-8TQ TQFP
IS61S6432-8PQ PQFP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Frequency (MHz) Order Part Number Package
117 IS61S6432-117TQI TQFP
IS61S6432-117PQI PQFP
100 IS61S6432-5TQI TQFP
IS61S6432-5PQI PQFP
83 IS61S6432-6TQI TQFP
IS61S6432-6PQI PQFP
75 IS61S6432-7TQI TQFP
IS61S6432-7PQI PQFP
66 IS61S6432-8TQI TQFP
IS61S6432-8PQI PQFP
NOTICE
Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user's specific application. While the information in this publication has been carefully checked, Integrated Silicon Solution, Inc.
shall not be liable for any damages arising as a result of any error or omission.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety
or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and
(c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.
Copyright 1998 Integrated Silicon Solution, Inc.
Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
®
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
19
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