Datasheet IS61LV6424-15TQ, IS61LV6424-12TQI, IS61LV6424-12TQ, IS61LV6424-10TQI, IS61LV6424-9TQI Datasheet (ISSI)
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FEATURES
• High-speed access time: 9, 10, 12, 15 ns
• CMOS low power operation
❑ 594 mW (max.) operating @ 9 ns
❑ 36 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Available in 100-pin TQFP
• Industrial temperature available
DESCRIPTION
The ISSI IS61LV6424 is a high-speed, static RAM organized
as 65,536 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields access times as fast as 9 ns with low power consumption.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE1, CE2, and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory.
The IS61LV6424 is packaged in the JEDEC standard
100-pin TQFP
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2000
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
IS61LV6424
64K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
ISSI
®
A0-A14
CE1
CE2
OE
WE
64K x 24
MEMORY ARRAY
ROW
DECODER
COLUMN
DECODER
I/O DATA
CIRCUIT
I/O0-I/O23
CONTROL
CIRCUIT
GND
V
CC
MULTIPLEX
ADDRESS
CONTROL
X/Y
A15
V/S
Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. A
12/19/00
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IS61LV6424
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PIN CONFIGURATION
100-Pin TQFP
PIN DESCRIPTIONS
A0-A14 Address Inputs
A15, X/Y Multiplexed Address
I/O0-I/O23 Data Inputs/Outputs
CE1, CE2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
V/S Address Multiplexer
NC No Connection
VCC Power
VCCQ Isolated Output Buffer Supply
GND Ground
GNDQ Isolated Output Buffer Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
NC
I/O12
I/O13
I/O14
I/O15
GNDQ
V
CCQ
I/O16
I/O17
NC
V
CC
NC
GND
I/O18
I/O19
V
CCQ
GNDQ
I/O20
I/O21
I/O22
I/O23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O11
I/O10
I/O9
I/O8
GNDQ
V
CCQ
I/O7
I/O6
GND
NC
V
CC
NC
I/O5
I/O4
V
CCQ
GNDQ
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
A13
A12
A11
A10
A9
A8
NC
NC
GND
V
CC
NC
NC
A7A6A5A4A3
A2
NC
A14
A15
CE1
CE2NCNCNCX/Y
V/S
V
CC
GNDNCWENCOENCNCNCA0
A1
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Integrated Silicon Solution, Inc. — 1-800-379-4774 3
Rev. A
12/19/00
OPERATING RANGE
Range Ambient Temperature VCC (9, 10 ns) VCC (12, 15 ns)
Commercial 0°C to +70°C 3.3V + 10%, – 5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V + 10%, – 5% 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage
(1)
–0.3 0.8 V
ILI Input Leakage GND - VIN - VCC –1 1 µA
ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –1 1 µA
Note:
1. V
IL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to 5.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to + 150 °C
TBIAS Temperature Under Bias: Com. –10 to + 85 °C
Ind. –45 to + 90 °C
PT Power Dissipation 2.0 W
IOUT DC Output Current ±20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode CE1 CE2 OE WE V/S I/O0-I/O23 Vcc Current
Not Selected H XXXX High-Z ISB1, ISB2
X L X X X High-Z
Read Using X/Y LHLHH DOUT ICC
Read Using A15 L H L H L DOUT ICC
Write Using X/Y LHXLH DIN ICC
Write Using A15 L H X L L DIN ICC
Output Disable L H H H X High-Z ICC
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4 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-9 ns -10ns -12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 165 — 150 — 125 — 100 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 170 — 155 — 130 — 105
I
SB1 TTL Standby Current VCC = Max., Com. — 40 — 40 — 35 — 30 mA
(TTL Inputs) VIN = VIH or VIL, f = max. Ind.—45—45—40—25
CE1 • VIH, CE2 - VIL
ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA
Current (CMOS Inputs) CE1 • VCC – 0.2V, Ind. — 15 — 15 — 15 — 15
CE2 - 0.2V, VIN • VCC – 0.2V,
or VIN - 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 2 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
OUTPUT
Z
O
= 50Ω
1.5V
50Ω
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
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Integrated Silicon Solution, Inc. — 1-800-379-4774 5
Rev. A
12/19/00
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-9 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 9 — 10 — 12 — 15 — ns
tAA Address Access Time — 9 — 10 — 12 — 15 ns
tAV V/S Access Time — 9 — 10 — 12 — 15 ns
tOH Output Hold Time 3 — 3 — 3 — 3 — ns
From MUX Change
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
From Address Change
tACE CE1Access Time — 9 — 10 — 12 — 15 ns
tACE2 CE2 Access Time
tDOE OE Access Time — 5 — 5 — 6 — 7 ns
tHZOE
(2)
OE to High-Z Output 0 3 0 3 0 3 0 3 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZCE
(2)
CE1 to High-Z Output 0 5 0 5 0 6 0 7 ns
tHZCE
2
(2)
CE2 to High-Z Output
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — 3 — ns
tLZCE
2
(2)
CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
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IS61LV6424
ISSI
®
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE1= OE = VIL; CE2 = VIH)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1= V
IL. CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transition.
t
AA
t
AA
DATA VALID
6424RD1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
AV
V/S
t
OH
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1
t
ACE2
t
LZCE1
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CE1
CE2
D
OUT
t
HZCE1
t
HZCE2
6424CE2_RD2.eps
V/S
t
AV
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Integrated Silicon Solution, Inc. — 1-800-379-4774 7
Rev. A
12/19/00
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-9 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 9 — 10 — 12 — 15 — ns
tSCE CE1 to Write End 7 — 7 — 8 — 10 — ns
tSCE
2
CE2 to Write End 7 — 7 — 8 — 10 —
tAW Address Setup Time 7 — 7 — 8 — 10 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tVS V/S Setup Time 0 — 0 — 0 — 0 — ns
tPWE1 WE Pulse Width (OE = HIGH) 7 — 7 — 8 — 10 — ns
tPWE2 WE Pulse Width (OE = LOW) 9 — 10 — 12 — 15 — ns
tSD Data Setup to Write End 5 — 5 — 6 — 7 — ns
tVW V/S to Write End 7 — 7 — 8 — 10 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
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IS61LV6424
ISSI
®
8 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
WRITE CYCLE NO. 1
(CE Controlled, OE = HIGH or LOW)
WRITE CYCLE NO. 2
(1)
(WE Controlled: OE = HIGH during Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE1
t
SCE2
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
DATAIN VALID
t
LZWE
t
SD
6424CE2_WR1.eps
V/S
t
VW
t
VS
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
HIGH
CE2
6424CE2_WR2.eps
V/S
t
VW
t
VS
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Integrated Silicon Solution, Inc. — 1-800-379-4774 9
Rev. A
12/19/00
WRITE CYCLE NO. 3
(1)
(WE Controlled: OE I S LOW
DURING WRITE CYLE
)
Note:
1. The internal Write time is defined by the overlap of CE1 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
HIGH
CE2
6424CE2_WR3.eps
t
VW
V/S
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IS61LV6424
ISSI
®
10 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
9 IS61LV6424-9TQ TQFP
10 IS61LV6424-10TQ TQFP
12 IS61LV6424-12TQ TQFP
15 IS61LV6424-15TQ TQFP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
9 IS61LV6424-9TQI TQFP
10 IS61LV6424-10TQI TQFP
12 IS61LV6424-12TQI TQFP
15 IS61LV6424-15TQI TQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
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