Datasheet IS61LV6416-8KI, IS61LV6416-8K, IS61LV6416-8B, IS61LV6416-8TI, IS61LV6416-20TI Datasheet (ISSI)

FEATURES

• High-speed access time: 8, 10, 12, 15, and 20 ns

• CMOS low power operation
— 250 mW (typical) operating
— 250 µW (typical) standby

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

IS61LV6416

64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

DESCRIPTION

The ISSI IS61LV6416 is a high-speed, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip
Enable and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and reading
of the memory.A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.

The IS61LV6416 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP, and 48-pin mini BGA
(6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

OCTOBER 2000

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

ISSI

®

A0-A15

CE
OE

WE

64K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

Integrated Silicon Solution, Inc.

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Rev. D

10/20/00

IS61LV6416

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Integrated Silicon Solution, Inc.

Rev. D

10/20/00

ISSI

®

PIN CONFIGURATIONS
44-Pin SOJ

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A15
A14
A13
A12
A11

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A10

A9
A8
A7

NC

A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A15
A14
A13
A12
A11

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A10

A9
A8
A7

NC

A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

44-Pin TSOP

48-Pin mini BGA (6mm x 8mm) PIN DESCRIPTIONS

A0-A15 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection
Vcc Power
GND Ground

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB

OE

A0

A1

A2

N/C

I/O

8

UB A3

A4

CE I/O

0

I/O

9

I/O10A5

A6

I/O1I/O

2

GND

I/O

11

NC

A7

I/O

3

Vcc

Vcc

I/O

12

NC

NC

I/O

4

GND

I/O

14

I/O

13

A14

A15

I/O

5

I/O

6

I/O

15

NC

A12

A13

WE

I/O

7

NC

A8

A9

A10

A11 NC

IS61LV6416

Integrated Silicon Solution, Inc.

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Rev. D

10/20/00

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OPERATING RANGE

Range Ambient Temperature Vcc(8,10ns) VCC (12,15,20NS)

Commercial 0°C to +70°C 3.3V+10%,-5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V+10%,-5% 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VCC + 0.3 V
VIL Input LOW Voltage

(1)

–0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC –22µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –22µA

Notes:

1. V

IL (min.) = –2.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

TRUTH TABLE

I/O PIN

Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z

Read H L L L H D

OUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

IS61LV6416

4

Integrated Silicon Solution, Inc.

Rev. D

10/20/00

ISSI

®

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns -20 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 8 — 10 — 12 — 15 — 20 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 — 20 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 — 20 ns
tDOE OE Access Time — 5 — 5 — 6 — 7 — 8ns
tHZOE

(2)

OE to High-Z Output — 5 — 5 — 60608ns

tLZOE

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — 0 — ns

tHZCE

(2

CE to High-Z Output 0 4 0 5 0 6 0 6 0 8 ns

tLZCE

(2)

CE to Low-Z Output 3 — 3 — 3 — 3 — 3 — ns

tBA LB, UB Access Time — 6 — 6 — 6 — 7 — 8ns
tHZB LB, UB to High-Z Output 0 4 0 5 0 6 0 6 0 8 ns
tLZB LB, UB to Low-Z Output 0 — 0 — 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns -20 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., Com. — 210 — 190 — 150 — 130 — 120 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 215 — 210 — 170 — 150 — 140

I

SB1 TTL Standby Current VCC = Max., Com. — 25 — 25 — 15 — 15 — 15 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 30 — 30 — 25 — 25 — 25

CE ≥ VIH , f = 0

I

SB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 — 10 mA

Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15 — 15

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

IS61LV6416

Integrated Silicon Solution, Inc.

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Rev. D

10/20/00

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AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1a and 1b

AC TEST LOADS

Figure 1a. Figure 1b.

319 Ω

30 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

319 Ω

5 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

IS61LV6416

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Integrated Silicon Solution, Inc.

Rev. D

10/20/00

ISSI

®

DATA VALID

READ1.eps

PREVIOUS DATA VALID

t

AA

t

OHA

t

OHA

t

RC

D

OUT

ADDRESS

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACE

t

LZCE

t

HZOE

HIGH-Z

DATA VALID

t

HZB

ADDRESS

OE

CE

LB, UB

D

OUT

t

HZCE

t

BA

t

LZB

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CS = OE = VIL, UB or LB = VIL)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

IL.

3. Address is valid prior to or coincident with CE LOW transition.

IS61LV6416

Integrated Silicon Solution, Inc.

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Rev. D

10/20/00

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WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns -20 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 8 — 10 — 12 — 15 — 20 — ns
tSCE CE to Write End 6 — 8 — 9 — 10 — 12 — ns
tAW Address Setup Time 8 — 8 — 9 — 10 — 12 — ns

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 7 — 8 — 9 — 10 — 12 — ns
tPWE WE Pulse Width 6 — 8 — 9 — 10 — 12 — ns
tSD Data Setup to Write End 6 — 6 — 6 — 7 — 9 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — 0 — ns
tHZWE

(2)

WE LOW to High-Z Output — 4 — 5 — 6 — 7 — 9ns

tLZWE

(2)

WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — 3 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.

IS61LV6416

8

Integrated Silicon Solution, Inc.

Rev. D

10/20/00

ISSI

®

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE)

[ (LB) = (UB) ] (WE).

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)

(1,2)

UNDEFINED UNDEFINED

t

WC

t

SCE

t

PWB

t

AW

t

HA

HIGH-ZHIGH-Z

t

PWE

t

HD

t

SA

t

HZWE

ADDRESS

CE

LB, UB

WE

WRITE

(1)

D

OUT

D

IN

t

LZWE

t

SD

IS61LV6416

Integrated Silicon Solution, Inc.

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Rev. D

10/20/00

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ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IS61LV6416-8B mini BGA (6mm x 8mm)
8 IS61LV6416-8T Plastic TSOP
8 IS61LV6416-8K

400-mil Plastic SOJ

10 IS61LV6416-10B mini BGA (6mm x 8mm)
10 IS61LV6416-10T Plastic TSOP
10 IS61LV6416-10K

400-mil Plastic SOJ

12 IS61LV6416-12B mini BGA (6mm x 8mm)
12 IS61LV6416-12T Plastic TSOP
12 IS61LV6416-12K

400-mil Plastic SOJ

15 IS61LV6416-15B mini BGA (6mm x 8mm)
15 IS61LV6416-15T Plastic TSOP
15 IS61LV6416-15K

400-mil Plastic SOJ

20 IS61LV6416-20B mini BGA (6mm x 8mm)
20 IS61LV6416-20T Plastic TSOP
20 IS61LV6416-20K

400-mil Plastic SOJ

IS61LV6416

10

Integrated Silicon Solution, Inc.

Rev. D

10/20/00

ISSI

®

ISSI

®

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

8 IS61LV6416-8BI mini BGA (6mm x 8mm)
8 IS61LV6416-8TI Plastic TSOP
8 IS61LV6416-8KI

400-mil Plastic SOJ

10 IS61LV6416-10BI mini BGA (6mm x 8mm)
10 IS61LV6416-10TI Plastic TSOP
10 IS61LV6416-10KI

400-mil Plastic SOJ

12 IS61LV6416-12BI mini BGA (6mm x 8mm)
12 IS61LV6416-12TI Plastic TSOP
12 IS61LV6416-12KI

400-mil Plastic SOJ

15 IS61LV6416-15BI mini BGA (6mm x 8mm)
15 IS61LV6416-15TI Plastic TSOP
15 IS61LV6416-15KI

400-mil Plastic SOJ

20 IS61LV6416-20BI mini BGA (6mm x 8mm)
20 IS61LV6416-20TI Plastic TSOP
20 IS61LV6416-20KI

400-mil Plastic SOJ