Datasheet IS61LV632A-8TQI, IS61LV632A-8PQI, IS61LV632A-8PQ, IS61LV632A-7TQI, IS61LV632A-7TQ Datasheet (ISSI)
...
IS61LV632A ISSI
®
32K x 32 SYNCHRONOUS FAST STATIC RAM
FEATURES
• Fast access time:
– 4 ns-125 MHz; 5 ns-100 MHz;
6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• 3.3V Vcc and 2.5V V
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or VCCQ to alter their power-up state
CCQ for 2.5V I/Os
DESCRIPTION
The ISSI IS61LV632A is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 32,768 words by 32 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally by the IS61LV632A and controlled by the ADV (burst
Q
address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
APRIL 2001
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
IS61LV632A ISSI
BLOCK DIAGRAM
MODE
CLK
ADV
ADSC
ADSP
CLK
BINARY
COUNTER
CE
CLR
Q0
Q1
A0
A1
A0'
A1'
32K x 32
MEMORY
ARRAY
®
A14-A0
GW
BWE
BW4
BW3
BW2
BW1
15
D
Q
13 15
ADDRESS
REGISTER
CE
CLK
D
Q
32
32
DQ32-DQ25
BYTE WRITE
REGISTERS
CLK
D
Q
DQ24-DQ17
BYTE WRITE
REGISTERS
CLK
D
Q
DQ16-DQ9
BYTE WRITE
REGISTERS
CLK
D
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE1
CE2
CE3
D
ENABLE
REGISTER
CE
CLK
D
Q
Q
4
REGISTERS
INPUT
CLK
OUTPUT
REGISTERS
CLK
OE
32
DATA[32:1]
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61LV632A ISSI
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
CE1
A6
A7
CE2
BW4
BW3
BW2
BW1
CE3
VCC
GND
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
NC
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
CLKGWBWEOEADSC
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
ADSP
ADVA8A9
46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
®
A5A4A3A2A1
MODE
A0
NC
NC
GND
VCC
PIN DESCRIPTIONS
A0-A14 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW4 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE1, CE2, CE3 Synchronous Chip Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
NC
NC
NC
A13
A14
NC
A10
A11
A12
OE Output Enable
DQ1-DQ32 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+2.5V
GNDQ Isolated Output Buffer Ground
3
IS61LV632A ISSI
TRUTH TABLE
ADDRESS
OPERATION USED CE1 CE2 CE3 ADSP ADSC ADV WR ITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X H L X X X High-Z
Deselected, Power-down None L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst External L H L L X X X H High-Z
Write Cycle, Begin Burst External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst External L H L H L X H H High-Z
Read Cycle, Continue Burst Next X X X H H L H L Q
Read Cycle, Continue Burst Next X X X H H L H H High-Z
Read Cycle, Continue Burst Next H X X X H L H L Q
Read Cycle, Continue Burst Next H X X X H L H H High-Z
Write Cycle, Continue Burst Next X X X H H L L X D
Write Cycle, Continue Burst Next H X X X H L L X D
Read Cycle, Suspend Burst Current X X X HHHHLQ
Read Cycle, Suspend Burst Current X X X HHHHHHigh-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X HHHHHigh-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
®
PARTIAL TRUTH TABLE
FUNCTION GW B W E BW1 BW2 BW3 BW4
READ H H X X X X
READ H X H H H H
WRITE Byte 1 H L L H H H
WRITE All Bytes X LLLLL
WRITE All Bytes L XXXXX
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61LV632A ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
0,1A1', A0' = 1,1
®
1,0
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.8 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 4.6 V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
(1)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5
IS61LV632A ISSI
OPERATING RANGE
Range Ambient Temperature VCC VCCQ
Commercial 0°C to +70°C 3.3V ±5% 2.375V min., 3.465V max.
Industrial –40°C to +85°C 3.3V ±5% 2.375V min., 3.465V max.
®
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –1.0 mA 2.0 — V
VOL Output LOW Voltage IOL = 1.0 mA — 0.4 V
VIH Input HIGH Voltage 1.7 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.7 V
I
LI Input Leakage Current GND - VIN - VCCQ
(2)
Com. –55µA
Ind. –10 10
ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. –55µA
Ind. –10 10
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-4-5-6-7-8
Sym. Parameter Test Conditions
ICC AC Operating Device Selected, Com. 150 180 140 170 130 160 120 150 110 140 mA
Supply Current All Inputs = VIL or VIH Ind. —— —— 140 170 130 160 120 150 mA
OE = VIH,
Cycle Time • tKC min.
ISB Standby Current Device Deselected, Com. 15 45 15 45 15 45 15 45 15 45 mA
VCC = Max., Ind. —— —— 20 50 20 50 20 50 mA
All Inputs = VIH or VIL
CLK Cycle Time • tKC min.
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Uni
t
IZZ Power-Down Mode ZZ = VCCQ, CLK Running Com. 1 10 1 10 1 10 1 10 1 10 mA
Current All Inputs - GND + 0.2V Ind. —— —— 220 220 220 mA
or • VCC – 0.2V
Note:
1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,
tied to GND, or tied to V
2. MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current
when tied to - GND + 0.2V or • Vcc – 0.2V.
6
CCQ.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61LV632A ISSI
®
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level for I/O Pins 0V to 2.5V
Input Pulse Level for Input Pins 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.25V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Z
Output
Buffer
O
= 50Ω
30 pF
Figure 1
1.25V
50Ω
2.5V
OUTPUT
5 pF
Including
jig and
scope
Figure 2
317 Ω
351 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
7
®
IS61LV632A ISSI
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8ns
(2)
t
KQX
tKQLZ
KQHZ
t
t
OEQ Output Enable to — 4 — 5 — 6 — 6 — 6ns
tOEQX
tOELZ
tOEHZ
Clock High to 1.5 — 1.5 — 2 — 2 — 2 — ns
Output Invalid
(2,3)
Clock High to 0 — 0 — 0 — 0 — 0 — ns
Output Low-Z
(2,3)
Clock High to 1.5 4 1.5 5 2 6 2 6 2 6 ns
Output High-Z
Output Valid
(2)
Output Disable to 0 — 0 — 0 — 0 — 0 — ns
Output Invalid
(2,3)
Output Enable to 0 — 0 — 0 — 0 — 0 — ns
Output Low-Z
(2,3)
Output Disable to — 4.5 — 4.8 — 6 — 6 — 6ns
Output High-Z
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
(1)
35 — 35 — 45 — 66.7 — 80 — ns
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
IS61LV632A ISSI
READ CYCLE TIMING
t
KC
CLK
t
KL
ADSP is blocked by CE1 inactive
ADSP
t
SS
t
SH
t
KH
®
ADSC
ADV
A14-A0
GW
BWE
BW4-BW1
CE1
CE2
t
AS
t
AH
RD1 RD2
t
WS
t
WS
t
CES
t
CES
t
CEH
t
CEH
t
SS
t
WH
t
WH
ADSC initiate read
t
AVS
t
SH
t
AVH
Suspend Burst
RD3
CE1 Masks ADSP
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
t
CES
t
CEH
CE3
t
t
OEQ
OEHZ
OE
t
OEQX
1a
DATA
OUT
DATA
IN
High-Z
High-Z
t
KQLZ
t
OELZ
t
KQ
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
2a 2b
Burst Read
2c 2d 3a
Pipelined Read
t
KQX
t
KQHZ
Unselected
9
IS61LV632A ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
t
SS Address Status 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
®
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
(1)
25 — 35 — 45 — 52 — 60 — ns
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Single Write
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A14-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61LV632A ISSI
WRITE CYCLE TIMING
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
11
®
IS61LV632A ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8ns
(2)
t
KQX
tKQLZ
KQHZ
t
t
OEQ Output Enable to — 4.5 — 4.8 — 6 — 6 — 6ns
tOEQX
tOELZ
tOEHZ
Clock High to 1.5 — 1.5 — 1.5 — 2 — 2 — ns
Output Invalid
(2,3)
Clock High to 0 — 0 — 0 — 0 — 0 — ns
Output Low-Z
(2,3)
Clock High to 1.5 4 1.5 5 1.5 5 2 6 2 6 ns
Output High-Z
Output Valid
(2)
Output Disable to 0 — 0 — 0 — 0 — ns
Output Invalid
(2,3)
Output Enable to 0 — 0 — 0 — 0 — ns
Output Low-Z
(2,3)
Output Disable to — 4.5 — 4.8 — 6 — 6 — 6ns
Output High-Z
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG Configuration Setup
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
(1)
25 — 35 — 45 — 52 — 60 — ns
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Single Read
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A14-A0
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE1 inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE3
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
IS61LV632A ISSI
READ/WRITE CYCLE TIMING
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
13
®
IS61LV632A ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8ns
(4)
t
KQX
tKQLZ
KQHZ
t
t
OEQ Output Enable to — 4.5 — 5 — 6 — 6 — 6ns
tOEQX
tOELZ
tOEHZ
Clock High to 1.5 — 1.5 — 2 — 2 — 2 — ns
Output Invalid
(4,5)
Clock High to 0 — 0 — 0 — 0 — 0 — ns
Output Low-Z
(4,5)
Clock High to 1.5 4 1.5 5 1.5 6 2 6 2 6 ns
Output High-Z
Output Valid
(4)
Output Disable to 0 — 0 — 0 — 0 — 0 — ns
Output Invalid
(4,5)
Output Enable to 0 — 0 — 0 — 0 — 0 — ns
Output Low-Z
(4,5)
Output Disable to — 4.5 — 4.8 — 6 — 6 — 6ns
Output High-Z
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
Setup Time
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Hold Time
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby
tZZREC ZZ Recovery
tCFG Configuration Setup
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with load in Figure 2.
(1)
(2)
2 — 2 — 2 — 2 — 2 — cyc
2 — 2 — 2 — 2 — 2 — cyc
(3)
25 — 35 — 45 — 52 — 60 — ns
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A14-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
ZZ
t
ZZS
t
ZZREC
IS61LV632A ISSI
SNOOZE AND RECOVERY CYCLE TIMING
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
15
IS61LV632A ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part Number Package
4 IS61LV632A-4TQ TQFP
4 IS61LV632A-4PQ PQFP
5 IS61LV632A-5TQ TQFP
5 IS61LV632A-5PQ PQFP
6 IS61LV632A-6TQ TQFP
6 IS61LV632A-6PQ PQFP
7 IS61LV632A-7TQ TQFP
7 IS61LV632A-7PQ PQFP
8 IS61LV632A-8TQ TQFP
8 IS61LV632A-8PQ PQFP
®
Industrial Range: –40°C to +85°C
Speed (ns) Order Part Number Package
6 IS61LV632A-6TQI TQFP
6 IS61LV632A-6PQI PQFP
7 IS61LV632A-7TQI TQFP
7 IS61LV632A-7PQI PQFP
8 IS61LV632A-8TQI TQFP
8 IS61LV632A-8PQI PQFP
®
ISSI
16
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Loading...