Datasheet IS61LV5128-15TI, IS61LV5128-15T, IS61LV5128-15KI, IS61LV5128-12K, IS61LV5128-12B Datasheet (ISSI)

IS61LV5128 ISSI

®

512K x 8 HIGH-SPEED CMOS STATIC RAM

FEATURES

• High-speed access times:
10, 12 and 15 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for
greater noise immunity

• Easy memory expansion with CE and OE
options

• CE power-down

• Fully static operation: no clock or refresh
required

• TTL compatible inputs and outputs

• Single 3.3V power supply

• Packages available:
– 36-pin 400-mil SOJ

– 36-pin miniBGA
– 44-pin TSOP (Type II)

DESCRIPTION

The ISSI IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The IS61LV5128
is fabricated using ISSI's high-performance CMOS tech­nology. This highly reliable process coupled with innova­tive circuit design techniques, yields higher performance
and low power consumption devices.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.

The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.

The IS61LV5128 is available in 36-pin 400-mil SOJ, 36­pin mini BGA, and 44-pin TSOP (Type II) packages.

JULY 2001

FUNCTIONAL BLOCK DIAGRAM

A0-A18

VCC

GND

I/O0-I/O7

CE

OE

WE

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

512K X 8

MEMORY ARRAY

COLUMN I/O

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

1

IS61LV5128 ISSI

1

2

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14

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18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

A0

A1

A2

A3

A4

CE

I/O0

I/O1

Vcc

GND

I/O2

I/O3

WE

A5

A6

A7

A8

A9

NC

A18

A17

A16

A15

OE

I/O7

I/O6

GND

Vcc

I/O5

I/O4

A14

A13

A12

A11

A10

NC

PIN CONFIGURATION

36 mini BGA

44-Pin TSOP (Type II)

®

1 2 3 4 5 6

A

B

C

D

E

F

G

H

A0

I/O4

I/O5

GND

Vcc

I/O6

I/O7

A9

A1

A2

OE

A10

PIN DESCRIPTIONS

NC

WE

NC

A18

CE

A11

A3

A4

A5

A17

A16

A12

A6

A7

A15

A13

A8

I/O0

I/O1

Vcc

GND

I/O2

I/O3

A14

NC
NC

A0
A1
A2
A3
A4

CE
I/O0
I/O1

Vcc

GND

I/O2
I/O3

WE

A5
A6
A7
A8

A9
NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

36-Pin SOJ

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC

A0-A18 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Bidirectional Ports

Vcc Power

GND Ground

NC No Connection

TRUTH TABLE

Mode WE CE OE I/O Operation Vcc Current

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC

Read H L L DOUT ICC

Write L L X DIN ICC

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

IS61LV5128 ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma­nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OPERATING RANGE

10 ns 12 ns, 15 ns

Range Ambient Temperature VCC VCC

Commercial 0°C to +70°C 3.3V +10%, -5% 3.3V ± 10%

Industrial –40°C to +85°C 3.3V +10%, -5% 3.3V ± 10%

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

CI/O Input/Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 3.3V.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

3

®

IS61LV5128 ISSI

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 V

VIL Input LOW Voltage

I

LI Input Leakage GND ≤ VIN ≤ VCC Com. –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –11µA

Note:

1. VIL = –3.0V for pulse width less than 10 ns.

(1)

–0.3 0.8 V

Ind. –55

Ind. –55

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-10 ns -12 ns -15 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Operating VCC = Max., CE = VIL Com. — 145 — 135 — 125 mA

Supply Current I OUT = 0 mA, f = fMAX. Ind. — 155 — 145 — 135

ISB TTL Standby VCC = Max., Com. — 70 — 60 — 50 mA

Current VIN = VIH or VIL Ind. — 80 — 70 — 60
(TTL Inputs) CE ≥ VIH, f = fMAX.

ISB1 TTL Standby VCC = Max., Com. — 20 — 20 — 20 mA

Current VIN = VIH or VIL Ind. — 25 — 25 — 25
(TTL Inputs) CE ≥ VIH, f = 0

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 mA

Current CE ≤ VCC – 0.2V, Ind. — 15 — 15 — 15
(CMOS Inputs) VIN ≥ VCC – 0.2V, or

VIN ≤ 0.2V, f = 0

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

IS61LV5128 ISSI

®

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-10 ns -12 ns -15 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 10 — 12 — 15 — ns

tAA Address Access Time — 10 — 12 — 15 ns

tOHA Output Hold Time 3 — 3 — 3 — ns
tACE CE Access Time — 10 — 12 — 15 ns
tDOE OE Access Time — 4 — 5 — 7ns

(2)

tLZOE

tHZOE

tLZCE

tHZCE

(2)

(2)

(2)

OE to Low-Z Output 0 — 0 — 0 — ns
OE to High-Z Output 0 4 0 5 0 6 ns
CE to Low-Z Output 3 — 3 — 3 — ns
CE to High-Z Output 0 4 0 6 0 8 ns

tPU Power Up Time 0 — 0 — 0 — ns
tPD Power Down Time — 10 — 12 — 15 ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Levels
Output Load See Figures 1 and 2

AC TEST LOADS

319 Ω

3.3V

OUTPUT

30 pF

Including

jig and

scope

353 Ω

3.3V

OUTPUT

5 pF

Including

jig and

scope

319 Ω

353 Ω

Figure 1 Figure 2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

5

IS61LV5128 ISSI

AC WAVEFORMS

(1,2)

READ CYCLE NO. 1

ADDRESS

(Address Controlled) (CE = OE = VIL)

t RC

®

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

CE

t

LZCE

D

OUT

HIGH-Z

PREVIOUS DATA VALID

(1,3)

(CE and OE Controlled)

t

AA

t

DOE

t

LZOE

t

ACE

t OHA

t

RC

t AA

DATA VALID

DATA VALID

t

HZCE

t OHA

t

OHA

t

READ1.eps

HZOE

CE_RD2.eps

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE = V

3. Address is valid prior to or coincident with CE LOW transitions.

IL.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

IS61LV5128 ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-10 ns -12 ns -15 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 10 — 12 — 15 — ns
tSCE CE to Write End 8 — 9 — 10 — ns

tAW Address Setup Time to 8 — 9 — 10 — ns

Write End

tHA Address Hold from 0 — 0 — 0 — ns

Write End

tSA Address Setup Time 0 — 0 — 0 — ns

(4)

tPWE1

WE Pulse Width 8 — 8 — 10 — ns

tPWE2 WE Pulse Width (OE = LOW) 10 — 12 — 12 — ns

tSD Data Setup to Write End 6 — 6 — 7 — ns

tHD Data Hold from Write End 0 — 0 — 0 — ns

(2)

tHZWE

(2)

tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.

4. Tested with OE HIGH.

WE LOW to High-Z Output 0 5 0 6 0 7 ns
WE HIGH to Low-Z Output 0 — 0 — 0 — ns

AC WAVEFORMS

WRITE CYCLE NO. 1

ADDRESS

CE

WE

D

OUT

D

IN

(1,2)

(CE Controlled, OE = HIGH or LOW)

t

VALID ADDRESS

t

SA

t

DATA UNDEFINED

t

AW

HZWE

t

PWE1

t

PWE2

t

WC

SCE

HIGH-Z

t

SD

DATAIN VALID

t

t

HD

t

LZWE

HA

CE_WR1.eps

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

7

IS61LV5128 ISSI

®

WRITE CYCLE NO. 2

ADDRESS

(1,2)

(WE Controlled: OE is HIGH During Write Cycle)

t

WC

VALID ADDRESS

t

HA

OE

CE

LOW

t

AW

t

PWE1

WE

t

SA

D

OUT

D

IN

DATA UNDEFINED

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.

2. I/O will assume the High-Z state if OE • V

IH.

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

LZWE

t

HD

CE_WR2.eps

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t

WC

ADDRESS

OE

CE

WE

OUT

D

D

IN

LOW

LOW

t

SA

DATA UNDEFINED

VALID ADDRESS

t

AW

t

PWE2

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

HA

t

LZWE

t

HD

CE_WR3.eps

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

IS61LV5128 ISSI

ORDERING INFORMATION

®

Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

10 IS61LV5128-10K 400-mil Plastic SOJ
10 IS61LV5128-10T TSOP (Type II)
10 IS61LV5128-10B mini BGA (8mmx10mm)

12 IS61LV5128-12K 400-mil Plastic SOJ
12 IS61LV5128-12T TSOP (Type II)
12 IS61LV5128-12B mini BGA (8mmx10mm)

15 IS61LV5128-15K 400-mil Plastic SOJ
15 IS61LV5128-15T TSOP (Type II)
15 IS61LV5128-15B mini BGA (8mmx10mm)

Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

10 IS61LV5128-10KI 400-mil Plastic SOJ
10 IS61LV5128-10TI TSOP (Type II)
10 IS61LV5128-10BI mini BGA (8mmx10mm)

12 IS61LV5128-12KI 400-mil Plastic SOJ
12 IS61LV5128-12TI TSOP (Type II)
12 IS61LV5128-12BI mini BGA (8mmx10mm)

15 IS61LV5128-15KI 400-mil Plastic SOJ
15 IS61LV5128-15TI TSOP (Type II)
15 IS61LV5128-15BI mini BGA (8mmx10mm)

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/16/01

®

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

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