• Single 3.3V + 10%, –5% power supply for 10
and 12 ns
• Single 3.3V ± 10% power supply for 15
and 20 ns
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin 400-mil SOJ package and
44-pin TSOP (Type II)
DESCRIPTION
The ISSI IS61LV3216L is a high-speed, 512K static RAM
organized as 32,768 words by 16 bits. It is fabricated using
ISSI's high-performance CMOS technology. This highly reli-
able process coupled with innovative circuit design techniques, yields fast access times with low power consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV3216L is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP (Type II).
LBLower-byte Control (I/O0-I/O7)
UBUpper-byte Control (I/O8-I/O15)
NCNo Connection
VccPower
GNDGround
TRUTH TABLE
I/O PIN
ModeWECEOEL BUBI/O0-I/O7I/O8-I/O15Vcc Current
Not SelectedXHXXXHigh-ZHigh-ZISB1, ISB2
Output DisabledHLHXXHigh-ZHigh-ZICC
XLXHHHigh-ZHigh-Z
ReadHLLLHDOUTHigh-ZICC
HLLHLHigh-ZDOUT
HLLLL DOUTDOUT
WriteLLXLHDINHigh-ZICC
LLXHLHigh-ZDIN
LLXLLDINDIN
2Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
IS61LV3216L
®
ISSI
ABSOLUTE MAXIMUM RATINGS
Symbol ParameterValueUnit
VCCSupply Voltage with Respect to GND–0.5 to +4.6V
VTERMTerminal Voltage with Respect to GND–0.5 to Vcc + 0.5V
TSTGStorage Temperature–65 to +150°C
PTPower Dissipation1.0W
IOUTDC Output Current (LOW)20mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
tBALB, UB Access Time—5—6—7—8ns
tHZBLB, UB to High-Z Output05060708ns
tLZBLB, UB to Low-Z Output5—5—5—5—ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
ParameterUnit
Input Pulse Level0V to 3.0V
Input Rise and Fall Times3 ns
Input and Output Timing1.5V
and Reference Level
Output LoadSee Figures 1a and 1b
AC TEST LOADS
3.3V
OUTPUT
30 pF
Including
jig and
scope
319 Ω
3.3V
OUTPUT
353 Ω
5 pF
Including
jig and
scope
319 Ω
353 Ω
Figure 1a.Figure 1b.
4Integrated Silicon Solution, Inc. — 1-800-379-4774
tWCWrite Cycle Time10—12—15—20—ns
tSCECE to Write End8—9—10—12—ns
tAWAddress Setup Time9—10—10—12—ns
to Write End
tHAAddress Hold from Write End1—1—1—1—ns
tSAAddress Setup Time0—0—0—0—ns
tPWBLB, UB Valid to End of Write9—10—11—12—ns
tPWEWE Pulse Width7—8—10—11—ns
tSDData Setup to Write End5—6—7——8ns
tHDData Hold from Write End0—0—0—0—ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
WE LOW to High-Z Output—5—6—7—8ns
(2)
WE HIGH to Low-Z Output1—1—1—1—ns
6Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
IS61LV3216L
AC WAVEFORMS
®
ISSI
WRITE CYCLE NO. 1 (WE Controlled)
ADDRESS
CE
LB, UB
WE
t
SA
WRITE
(1)
(1,2)
t
AW
t
SCE
t
PWB
t
t
PWE
WC
t
1
2
HA
3
4
5
6
t
t
SD
D
IN
t
HZWE
D
OUT
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE)
[ (LB) = (UB) ] (WE).
UNDEFINEDUNDEFINED
HD
t
LZWE
HIGH-ZHIGH-Z
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-47747
Rev. A
12/19/00
IS61LV3216L
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.Package
10IS61LV3216L-10TPlastic TSOP (Type II)
IS61LV3216L-10K400-mil Plastic SOJ
12IS61LV3216L-12TPlastic TSOP (Type II)
IS61LV3216L-12K400-mil Plastic SOJ
15IS61LV3216L-15TPlastic TSOP (Type II)
IS61LV3216L-15K400-mil Plastic SOJ
20IS61LV3216L-20TPlastic TSOP (Type II)
IS61LV3216L-20K400-mil Plastic SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.Package
12IS61LV3216L-12TI Plastic TSOP (Type II)
IS61LV3216L-12KI 400-mil Plastic SOJ
15IS61LV3216L-15TI Plastic TSOP (Type II)
IS61LV3216L-15KI 400-mil Plastic SOJ
20IS61LV3216L-20TI Plastic TSOP (Type II)
IS61LV3216L-20KI 400-mil Plastic SOJ
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
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