Datasheet IS61LV3216-20T, IS61LV3216-20KI, IS61LV3216-20K, IS61LV3216-15TI, IS61LV3216-15KI Datasheet (ISSI)

IS61LV3216 ISSI

®

32K x 16 LOW VOLTAGE CMOS STATIC RAM

FEATURES

• High-speed access time: 10, 12, 15, and 20 ns

• CMOS low power operation
— 150 mW (typical) operating
— 150 µW (typical) standby

• TTL compatible interface levels

• Single 3.3V ± 10% power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Industrial temperature available

• Available in 44-pin 400-mil SOJ package and
44-pin TSOP (Type 2)

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ISSI IS61LV3216 is a high-speed, 512K static RAM
organized as 32,768 words by 16 bits. It is fabricated using

ISSI's high-performance CMOS technology. This highly reli-

able process coupled with innovative circuit design tech­niques, yields fast access times with low power consumption.

When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.

The IS61LV3216 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP (Type 2).

NOVEMBER 1997

A0-A14

VCC

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE

OE
WE

UB

LB

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

32K x 16

MEMORY ARRAY

COLUMN I/O

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

1

IS61LV3216 ISSI

®

PIN CONFIGURATIONS

44-Pin SOJ

NC

A14

A13

A12

A11

CE

I/O0

I/O1

I/O2

I/O3

Vcc

GND

I/O4

I/O5

I/O6

I/O7

WE

A10

A9

A8

A7

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A0

A1

A2

OE
UB
LB

I/O15

I/O14

I/O13

I/O12

GND

Vcc

I/O11

I/O10

I/O9

I/O8

NC

A3

A4

A5

A6

NC

44-Pin TSOP

NC
A14
A13
A12
A11

CE

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A10

A9
A8
A7

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

PIN DESCRIPTIONS

A0-A14 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

TRUTH TABLE

I/O PIN

Mode WE CE OE L B UB I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

IS61LV3216 ISSI

®

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC Supply Voltage with Respect to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
IOUT DC Output Current (LOW) 20 mA

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

(1)

Note:

1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec­tions of this specification is not im­plied. Exposure to absolute maximum
rating conditions for extended periods
may affect reliability.

1

2

3

4

5

VIH Input HIGH Voltage 2.2 VCC + 0.3 V

VIL Input LOW Voltage

ILI Input Leakage GND - VIN - VCC –22µA

ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –22µA

Notes:

1. VIL (min.) = –3.0V for pulse width less than 10 ns.

(1)

–0.3 0.8 V

6

7

8

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., Com. — 220 — 200 — 180 — 160 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. —— —230 — 200 — 180

ISB1 TTL Standby Current VCC = Max., Com. — 10 — 10 — 10 — 10 mA

(TTL Inputs) VIN = VIH or VIL Ind. —— —20 — 20 — 20

CE • VIH , f = 0

ISB2 CMOS Standby VCC = Max., Com. — 5 — 5 — 5 — 5mA

Current (CMOS Inputs) CE • VCC – 0.2V, Ind. —— —10 — 10 — 10

VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0

(1)

(Over Operating Range)

-10 ns -12 ns -15 ns -20 ns

9

10

11

12

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

3

IS61LV3216 ISSI

®

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-10 -12 -15 -20

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 10 — 12 — 15 — 20 — ns

tAA Address Access Time — 10 — 12 — 15 — 20 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 10 — 12 — 15 — 20 ns
tDOE OE Access Time — 5 — 6 — 7 — 8ns

(2)

tHZOE

tLZOE

tHZCE

tLZCE

OE to High-Z Output 0 5 0 6 0 7 0 8 ns

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

(2

CE to High-Z Output 0 5 0 6 0 7 0 8 ns

(2)

CE to Low-Z Output 4 — 4 — 4 — 4 — ns

tBA LB, UB Access Time — 5 — 6 — 7 — 8ns
tHZB LB, UB to High-Z Output 0 5 0 6 0 7 0 8 ns
tLZB LB, UB to Low-Z Output 5 — 5 — 5 — 5 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1a and 1b

AC TEST LOADS

3.3V

OUTPUT

30 pF

Including

jig and

scope

319 Ω

3.3V

OUTPUT

353 Ω

5 pF

Including

jig and

scope

319 Ω

353 Ω

Figure 1a. Figure 1b.

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

IS61LV3216 ISSI

AC WAVEFORMS

®

READ CYCLE NO. 1

ADDRESS

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

PREVIOUS DATA VALID

(1,3)

t

AA

t

RC

DATA VALID

t

OHA

t

1

2

3

4

5

OHA

6

t

DOE

t

CE

t

LZCE

LB, UB

t

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transition.

HIGH-Z

LZB

LZOE

t

ACE

t

BA

t

HZOE

7

t

HZCE

8

t

HZB

DATA VALID

9

IL.

10

11

12

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

5

IS61LV3216 ISSI

®

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-10 -12 -15 -20

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 10 — 12 — 15 — 20 — ns
tSCE CE to Write End 9 — 10 — 11 — 12 — ns

tAW Address Setup Time 9 — 10 — 11 — 12 — ns

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 9 — 10 — 11 — 12 — ns
tPWE WE Pulse Width 7 — 8 — 10 — 11 — ns

tSD Data Setup to Write End 5 — 6 — 7 ——8ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

(2)

tHZWE

tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

WE LOW to High-Z Output — 5 — 6 — 7 — 8ns

(2)

WE HIGH to Low-Z Output 1 — 1 — 1 — 1 — ns

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

IS61LV3216 ISSI

AC WAVEFORMS

®

WRITE CYCLE NO. 1 (WE Controlled)

ADDRESS

CE

LB, UB

WE

t

SA

WRITE

(1)

(1,2)

t

AW

t

SCE

t

PWB

t

t

PWE

WC

t

1

2

HA

3

4

5

6

t

t

SD

D

IN

t

HZWE

D

OUT

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE)

[ (LB) = (UB) ] (WE).

UNDEFINED UNDEFINED

HD

t

LZWE

HIGH-ZHIGH-Z

7

8

9

10

11

12

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

7

IS61LV3216 ISSI

®

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

10 IS61LV3216-10T Plastic TSOP (Type 2)
10 IS61LV3216-10K 400-mil Plastic SOJ

12 IS61LV3216-12T Plastic TSOP (Type 2)
12 IS61LV3216-12K 400-mil Plastic SOJ

15 IS61LV3216-15T Plastic TSOP (Type 2)
15 IS61LV3216-15K 400-mil Plastic SOJ

20 IS61LV3216-20T Plastic TSOP (Type 2)
20 IS61LV3216-20K 400-mil Plastic SOJ

NOTICE

Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits
are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may
vary depending upon a user's specific application. While the information in this publication has been carefully checked,
Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission.

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

12 IS61LV3216-12TI Plastic TSOP (Type 2)
12 IS61LV3216-12KI 400-mil Plastic SOJ

15 IS61LV3216-15TI Plastic TSOP (Type 2)
15 IS61LV3216-15KI 400-mil Plastic SOJ

20 IS61LV3216-20TI Plastic TSOP (Type 2)
20 IS61LV3216-20KI 400-mil Plastic SOJ

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect
its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc.
receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes
all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.

Copyright 1997 Integrated Silicon Solution, Inc.

Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

®

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01