Page 1
IS61LV256AL ISSI
®
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FEATURES
• High-speed access times:
— 10 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 60 µW (typical) CMOS standby
— 65 mW (typical) operating
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Lead-free available
MARCH 2006
DESCRIPTION
The ISSI IS61LV256AL is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256AL is available in the JEDEC standard 28pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VDD
GND
I/O0-I/O7
CE
OE
WE
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
1
Page 2
IS61LV256AL ISSI
®
PIN CONFIGURATION
28-Pin SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
28-Pin TSOP (Type I)
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
9
A1
8
A2
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
TRUTH TABLE
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
CECE
CE
CECE
OEOE
OE I/O Operation VDD Current
OEOE
VDD Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VDD Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
Page 3
IS61LV256AL ISSI
OPERATING RANGE
Range Ambient Temperature Speed (ns) VDD
Commercial 0°C to +70°C 10 3.3V, +10%, –5%
Industrial –40°C to +85°C 10 3.3V + 10%, –5%
Note: 1. If operated at 12ns, VDD range is 3.3V + 10%.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
(1)
(1)
–0.3 0.8 V
Ind. –2 2
®
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –1 1 µA
Ind. –2 2
Notes:
IL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
1. V
VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
3
Page 4
IS61LV256AL ISSI
®
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
Sym. Parameter Test Conditions Min. Max. Unit
ICC1VDD Operating VDD = Max., CE = VIL Com. — 20 mA
Supply Current I OUT = 0 mA, f = 1 MHz Ind. — 25
ICC2VDD Dynamic Operating VDD = Max., CE = VIL Com. — 30 mA
Supply Current I OUT = 0 mA, f = fMAX Ind. — 35
(2)
typ.
SB1 TTL Standby Current VDD = Max., Com. — 1 mA
I
20
(TTL Inputs) VIN = VIH or VIL Ind. — 1
CE ≥ VIH , f = 0
I
SB2 CMOS Standby VDD = Max., Com. — 40 µA
Current (CMOS Inputs) CE ≤ V DD – 0.2V, Ind. — 50
VIN ≥ V DD – 0.2V, or typ.
(2)
2
VIN ≤ 0.2V, f = 0
Notes:
1. At f = f
2. Typical values are measured at V
CAPACITANCE
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DD = 3.3V, TA = 25
(1,2)
o
C and not 100% tested.
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
Page 5
IS61LV256AL ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — ns
tAA Address Access Time — 10 — 12 ns
tOHA Output Hold Time 2 — 2 — ns
tACE CE Access Time — 10 — 12 ns
tDOE OE Access Time — 5 — 5 ns
(2)
tLZOE
(2)
tHZOE
(2)
tLZCE
(2)
tHZCE
(3)
tPU
(3)
tPD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
OE to Low-Z Output 0 — 0 — ns
OE to High-Z Output — 5 — 5 ns
CE to Low-Z Output 3 — 3 — ns
CE to High-Z Output — 5 — 6 ns
CE to Power-Up 0 — 0 — ns
CE to Power-Down — 10 — 12 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
5 pF
Including
jig and
scope
319 Ω
353 Ω
Figure 1. Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
5
Page 6
IS61LV256AL ISSI
AC WAVEFORMS
®
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
PREVIOUS DATA VALID
(1,3)
t
AA
t
OHA
t
RC
t
AA
DATA VALID
t
RC
t
OHA
t
OHA
READ1.eps
t
DOE
t
LZOE
t
ACE
D
CE
OUT
t
LZCE
HIGH-Z
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL.
3. Address is valid prior to or coincident with CE LOW transitions.
DATA VALID
t
HZCE
t
HZOE
CE_RD2.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
Page 7
IS61LV256AL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 10 — 12 — ns
tSCE CE to Write End 8 — 8 — ns
tAW Address Setup Time 8 — 8 — ns
to Write End
tHA Address Hold 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — ns
tPWE1 WE Pulse Width (OE HIGH) 7 — 8 — ns
tPWE2 WE Pulse Width (OE LOW) 10 — 12 — ns
tSD Data Setup to Write End 6.5 — 7 — ns
tHD Data Hold from Write End 0 — 0 — ns
(3)
tHZWE
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
WE LOW to High-Z Output — 3.5 — 5 ns
WE HIGH to Low-Z Output 0 — 0 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1
ADDRESS
CE
WE
OUT
D
D
IN
(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
t
SA
t
DATA UNDEFINED
t
AW
HZWE
t
PWE1
t
PWE2
t
SCE
(1 )
HIGH-Z
t
SD
DATA
IN
VALID
t
HA
t
LZWE
t
HD
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
7
Page 8
IS61LV256AL ISSI
®
WRITE CYCLE NO. 2
ADDRESS
OE
CE
LOW
WE
t SA
OUT
D
D
IN
(WE Controlled, OE is HIGH During Write Cycle)
t WC
VALID ADDRESS
t AW
t PWE1
t HZWE
DATA UNDEFINED
HIGH-Z
t SD
DATAIN VALID
(1,2)
t HA
t LZWE
t HD
CE_WR2.eps
WRITE CYCLE NO. 3
ADDRESS
LOW
OE
CE
LOW
(WE Controlled, OE is LOW During Write Cycle)
t
WC
VALID ADDRESS
t
AW
t
PWE2
(1)
t
HA
WE
t
SA
OUT
D
D
IN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > V
DATA UNDEFINED
IH.
t
HZWE
HIGH-Z
t
SD
DATAIN VALID
t
LZWE
t
HD
CE_WR3.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
Page 9
IS61LV256AL ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
®
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.0 3.6 V
IDR Data Retention Current VDD = 2.0V, CE ≥ V DD – 0.2V Com. — 2 40 µA
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
Ind. — — 50
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
Note:
1. Typical Values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (
t
SDR
VDD
V
DR
CE
GND
CECE
CE Controlled)
CECE
Data Retention Mode
CE ≥ VDD
- 0.2V
t
RDR
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
9
Page 10
IS61LV256AL ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
10 IS61LV256AL-10T TSOP - Type I
IS61LV256AL-10TL TSOP - Type I, Lead-free
IS61LV256AL-10J 300-mil Plastic SOJ
IS61LV256AL-10JL 300-mil Plastic SOJ, Lead-free
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61LV256AL-10TI TSOP - Type I
IS61LV256AL-10TLI TSOP - Type I, Lead-free
IS61LV256AL-10JI 300-mil Plastic SOJ
IS61LV256AL-10JLI 300-mil Plastic SOJ, Lead-free
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
Page 11
PACKAGING INFORMATION ISSI
300-mil Plastic SOJ
Package Code: J
N
®
E1
1
E
D
A
B
e
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 24/26
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 17.02 — 17.27 0.670 — 0.680
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
b
A1
SEATING PLANE
E2
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and
the package
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
A2
C
should be measured from the bottom of
.
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. D
02/25/03
1-800-379-4774
Page 12
PACKAGING INFORMATION ISSI
300-mil Plastic SOJ
Package Code: J
®
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 28
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 18.29 — 18.54 0.720 — 0.730
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 32
A — — 3.56 — — 0.140
A1 0.64 — — 0.025 — —
A2 2.41 — 2.67 0.095 — 0.105
b 0.41 — 0.51 0.016 — 0.020
B 0.66 — 0.81 0.026 — 0.032
C 0.20 — 0.25 0.008 — 0.010
D 20.83 — 21.08 0.820 — 0.830
E 8.26 — 8.76 0.325 — 0.345
E1 7.49 — 7.75 0.295 — 0.305
E2 6.27 — 7.29 0.247 — 0.287
e 1.27 BSC 0.050 BSC
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/25/03
Page 13
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
®
ISSI
E
H
N
D
S
e
B
Plastic TSOP (T—Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
No. Leads 28
A 1.00 1.20 0.037 0.047
A1 0.05 0.20 0.002 0.008
B 0.16 0.27 0.006 0.011
C 0.10 0.20 0.004 0.008
D 7.90 8.10 0.308 0.316
E 11.70 11.90 0.456 0.465
H 13.20 13.60 0.515 0.531
e 0.55 BSC 0.022 BSC
L 0.30 0.70 0.011 0.027
α 0° 5° 0° 5°
A
SEATING PLANE
L
A1
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
α
C
.
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97
Loading...