Datasheet IS61LV2568-8T, IS61LV2568-8KI, IS61LV2568-8K, IS61LV2568-15T, IS61LV2568-15KI Datasheet (ISSI)

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

IS61LV2568

256K x 8 HIGH-SPEED CMOS STATIC RAM

DECEMBER 2000

FEATURES

• High-speed access times:
8, 10, 12 and 15 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for
greater noise immunity

• Easy memory expansion with CE and OE
options

• CE power-down

• Low power: 540 mW @ 10 ns
36 mW standby mode

• TTL compatible inputs and outputs

• Single 3.3V ±10% power supply

• Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)

DESCRIPTION

The ISSI IS61LV2568 is a very high-speed, low power,
262,144-word by 8-bit CMOS static RAM. The IS61LV2568
is fabricated using ISSI's high-performance CMOS tech­nology. This highly reliable process coupled with innova­tive circuit design techniques, yields higher performance
and low power consumption devices.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.

The IS61LV2568 operates from a single 3.3V power
supply and all inputs are TTL-compatible.

The IS61LV2568 is available in 36-pin 400-mil SOJ, and
44-pin TSOP (Type II) packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A17

CE

OE

WE

256K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774 1

Rev. A

12/19/00

IS61LV2568

ISSI

®

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

PIN CONFIGURATION

36-Pin SOJ

PIN DESCRIPTIONS

A0-A17 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Bidirectional Ports

Vcc Power

GND Ground

NC No Connection

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VCC Supply voltage with Respect to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias Com. –10 to +85 °C

Ind. –45 to +90
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TRUTH TABLE

Mode WE CE OE I/O Operation Vcc Current

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC

Read H L L DOUT ICC

Write L L X DIN ICC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

A4

A3

A2

A1

A0

CE

I/O0

I/O1

Vcc

GND

I/O2

I/O3

WE

A17

A16

A15

A14

A13

NC

A5

A6

A7

A8

OE

I/O7

I/O6

GND

Vcc

I/O5

I/O4

A9

A10

A11

A12

NC

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC

A4
A3
A2
A1
A0

CE
I/O0
I/O1

Vcc

GND

I/O2
I/O3

WE
A17
A16
A15
A14
A13

NC
NC

NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC

44
43
42
41

44-Pin TSOP (Type II)

IS61LV2568

ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774 3

Rev. A

12/19/00

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

VIH Input HIGH Voltage

(1)

2.0 VCC + 0.3 V

VIL Input LOW Voltage

(1)

–0.3 0.8 V

I

LI Input Leakage GND - VIN - VCC Com. –1 1 µA

Ind. –5 5

ILO Output Leakage GND - VOUT - VCC, Outputs Disabled Com. –1 1 µA

Ind. –5 5

Note:

1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
V

IH(max) = VCC + 0.3V (DC); VIH(max) = Vcc + 2.0V (pulse width - 2.0 ns).

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

CI/O Input/Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 3.3V.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Operating VCC = Max., CE = VIL Com. — 150 — 125 — 110 — 90 mA

Supply Current IOUT = 0 mA, f = Max. Ind. — 160 — 135 — 120 — 100

ISB1 TTL Standby VCC = Max., Com. — 50 — 40 — 35 — 30 mA

Current VIN = VIH or VIL Ind. — 60 — 50 — 45 — 40
(TTL Inputs) CE • VIH, f = max

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA

Current CE - VCC – 0.2V, Ind. — 20 — 20 — 20 — 20
(CMOS Inputs) VIN > VCC – 0.2V, or

VIN - 0.2V, f = 0

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

IS61LV2568

ISSI

®

4 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

AC TEST LOADS

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Levels
Output Load See Figures 1 and 2

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

- 8 ns -10 ns -12 ns -15 ns

Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 8 — 10 — 12 — 15 — ns

tAA Address Access Time — 8 — 10 — 12 — 15 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 3 — 4 — 5 — 6 ns

tLZOE

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

tHZOE

(2)

OE to High-Z Output 0 3 0 4 0 5 0 6 ns

tLZCE

(2)

CE to Low-Z Output 3 — 3 — 3 — 3 — ns

tHZCE

(2)

CE to High-Z Output 0 3 0 4 0 5 0 6 ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

Figure 1 Figure 2

319 Ω

30 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

319 Ω

5 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

IS61LV2568

ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774 5

Rev. A

12/19/00

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACE

t

LZCE

t

HZOE

HIGH-Z

DATA VALID

CE_RD2.eps

ADDRESS

OE

CE

D

OUT

t

HZCE

READ CYCLE NO. 2

(1,3)

(CE and OE Controlled)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE = V

IL.

3. Address is valid prior to or coincident with CE LOW transitions.

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CE = OE = VIL)

DATA VALID

READ1.eps

PREVIOUS DATA VALID

t

AA

t

OHA

t

OHA

t

RC

D

OUT

ADDRESS

IS61LV2568

ISSI

®

6 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

- 8 ns -10 ns -12 ns -15 ns

Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 6.5 — 8 — 9 — 10 — ns

tAW Address Setup Time to 6.5 — 8 — 9 — 10 — ns

Write End

tHA Address Hold from 0 — 0 — 0 — 0 — ns

Write End

tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE1 WE Pulse Width (OE = HIGH) 5 — 7 — 8 — 10 — ns
tPWE2 WE Pulse Width (OE = LOW) 6.5 — 8 — 10 — 11 — ns

tSD Data Setup to Write End 4 — 5 — 6 — 7 — ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

tHZWE

(3)

WE LOW to High-Z Output — 3 — 4 — 5 — 6 ns

tLZWE

(3)

WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS
WRITE CYCLE NO. 1

(1,2)

(CE Controlled, OE = HIGH or LOW)

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCE

t

PWE1

t

PWE2

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE

WE

D

OUT

D

IN

DATAIN VALID

t

LZWE

t

SD

CE_WR1.eps

Note:

1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any

can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.

IS61LV2568

ISSI

®

Integrated Silicon Solution, Inc. — 1-800-379-4774 7

Rev. A

12/19/00

WRITE CYCLE NO. 2

(1)

(WE Controlled, OE = HIGH during Write Cycle)

Note:

1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any

can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.

DATA UNDEFINED

LOW

t

WC

VALID ADDRESS

t

PWE1

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

CE_WR2.eps

AC WAVEFORMS

WRITE CYCLE NO. 3

(WE Controlled: OE is LOW During Write Cycle)

Note:

1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any

can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.

DATA UNDEFINED

t

WC

VALID ADDRESS

LOW

LOW

t

PWE2

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

CE_WR3.eps

IS61LV2568

ISSI

®

8 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

ISSI

®

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IS61LV2568-8K 400-mil Plastic SOJ

IS61LV2568-8T TSOP (Type II)

10 IS61LV2568-10K 400-mil Plastic SOJ

IS61LV2568-10T TSOP (Type II)

12 IS61LV2568-12K 400-mil Plastic SOJ

IS61LV2568-12T TSOP (Type II)

15 IS61LV2568-15K 400-mil Plastic SOJ

IS61LV2568-15T TSOP (Type II)

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

8 IS61LV2568-8KI 400-mil Plastic SOJ

IS61LV2568-8TI TSOP (Type II)

10 IS61LV2568-10KI 400-mil Plastic SOJ

IS61LV2568-10TI TSOP (Type II)

12 IS61LV2568-12KI 400-mil Plastic SOJ

IS61LV2568-12TI TSOP (Type II)

15 IS61LV2568-15KI 400-mil Plastic SOJ

IS61LV2568-15TI TSOP (Type II)