Datasheet IS61LV25616-15BI, IS61LV25616-15B, IS61LV25616-12LQI, IS61LV25616-12LQ, IS61LV25616-12KI Datasheet (ISSI)
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IS61LV25616 ISSI
256K x 16 HIGH SPEED ASYNCHRONOUS
®
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
• High-speed access time:
— 7, 8, 10, 12, and 15 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 m
A (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption
devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV25616 is packaged in the JEDEC standard
44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and
48-pin Mini BGA (8mm x 10mm).
AUGUST 2000
A0-A17
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256K x 16
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
1
IS61LV25616 ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ 44-Pin LQFP
44
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
A17
A16
A15
A14
A13
A12
A11
A10OEUB
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
TOP VIEW
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
A0A1A2A3A4A5A6A7A8
WE
LB
33
32
31
30
29
28
27
26
25
24
23
A9
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
®
48-Pin mini BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
I/O
I/O
GND
Vcc
I/O
I/O
NC
8
9
14
15
OE
UB A3
I/O10A5
I/O
11
I/O
12
I/O
13
NC
A8
A0
A17
NC
A14
A12
A9
A16
A15
A13
A1
A4
A6
A7
A10
A2
N/C
CE I/O
I/O1I/O
I/O
3
I/O
GND
4
I/O
I/O
5
WE
I/O
A11 NC
Vcc
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
0
2
6
7
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616 ISSI
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H D
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
OUT High-Z ICC
®
1
2
3
4
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias –45 to +90 °C
VCC Vcc Related to GND –0.3 to +4.0 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature VCC VCC
(1)
7, 8, 10 ns 12 ns, 15 ns
5
6
7
8
9
10
11
Commercial 0°C to +70°C 3.3V +10%, -5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V +10%, -5% 3.3V ± 10%
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
12
3
®
IS61LV25616 ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –11µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, 4 Com. –11µA
Notes:
IL (min.) = –2.0V for pulse width less than 10 ns.
1. V
(1)
–0.3 0.8 V
Ind. –55
Outputs Disabled Ind. –55
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-7, -8 -10 -12 -15
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 260 — 260 — 240 — 220 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 300 — 300 — 280 — 250
ISB TTL Standby Current VCC = Max., Com. — 85 — 85 — 75 — 65 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 95 — 95 — 85 — 75
CE ≥ VIH, f = fMAX.
ISB1 TTL Standby Current VCC = Max., Com. — 20 — 20 — 20 — 20 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 25 — 25 — 25 — 25
CE ≥ VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA
Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Shaded area product in development
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616 ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS
-7 -8 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 7 — 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 7 — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 7 — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 3.5 — 3.5 — 4 — 5 — 7ns
(2)
tHZOE
tLZOE
tHZCE
tLZCE
tBA LB, UB Access Time — 3 — 3.5 — 4 — 5 — 7ns
(2)
tHZB
(2)
tLZB
tPU Power Up Time 0 — 0 — 0 — 0 — 0 — ns
tPD Power Down Time — 7 — 8 — 10 — 12 — 15 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,
input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Shaded area product in development
OE to High-Z Output — 2.5 — 3 — 4 — 506ns
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — 0 — ns
(2
CE to High-Z Output 0 3 — 3040608ns
(2)
CE to Low-Z Output 2.5 — 3 — 3 — 3 — 3 — ns
LB, UB to High-Z Output 0 2.5 0 3 0 3 0 4 0 5 ns
LB, UB to Low-Z Output 0 — 0 — 0 — 0 — 0 — ns
(1)
(Over Operating Range)
1
2
3
4
5
6
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
ZO = 50Ω
OUTPUT
50Ω
1.5V
30 pF
Including
jig and
scope
3.3V
OUTPUT
5 pF
Including
jig and
scope
7
8
9
10
319 Ω
11
353 Ω
12
Figure 1 Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
5
IS61LV25616 ISSI
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
(1,2)
(Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
t
AA
t
OHA
t
OHA
®
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
CE
LB, UB
PREVIOUS DATA VALID
(1,3)
t
LZCE
DATA VALID
READ1.eps
t
RC
t
AA
t
DOE
t
LZOE
t
ACE
t
HZCE
t
OHA
t
HZOE
t
BA
t
D
OUT
V
Supply
Current
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = V
3. Address is valid prior to or coincident with CE LOW transition.
HIGH-Z
CC
LZB
t
PU
50%
6
t
t
RC
DATA VALID
t
PD
IL.
HZB
50%
I
CC
I
SB
UB_CEDR2.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616 ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
-7 -8 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 7 — 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 5 — 5.5 — 8 — 8 — 10 — ns
tAW Address Setup Time 5 — 5.5 — 8 — 8 — 10 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 5 — 5.5 — 8 — 8 — 10 — ns
tPWE1 WE Pulse Width 5 — 5.5 — 8 — 8 — 10 — ns
tPWE2 WE Pulse Width (OE = LOW) 7 — 5 — 10 — 12 — 12 — ns
tSD Data Setup to Write End 3.5 — 4 — 6 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Shaded area product in development
WE LOW to High-Z Output — 3 — 3.5 — 5 — 6 — 7ns
(2)
WE HIGH to Low-Z Output 2 — 2 — 2 — 2 — 2 — ns
(1,3)
(Over Operating Range)
1
2
3
4
5
6
7
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
8
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7
IS61LV25616 ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
t
(1 )
WC
®
ADDRESS
t
SA
VALID ADDRESS
t
SCE
t
HA
CE
t
AW
t
PWE1
t
WE
PWE2
t
PBW
UB, LB
t
HZWE
D
OUT
D
IN
DATA UNDEFINED
HIGH-Z
t
SD
DATAIN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE)
[ (LB) = (UB) ] (WE).
t
t
HD
LZWE
UB_CEWR1.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616 ISSI
AC WAVEFORMS
®
WRITE CYCLE NO. 2
ADDRESS
OE
CE
WE
UB, LB
OUT
D
DIN
(WE Controlled. OE is HIGH During Write Cycle)
t
WC
VALID ADDRESS
LOW
t
AW
t
PWE1
t
SA
DATA UNDEFINED
t
HZWE
t
PBW
HIGH-Z
t
SD
DATAIN VALID
(1,2)
1
t
HA
2
3
4
t
LZWE
5
t
HD
UB_CEWR2.eps
6
WRITE CYCLE NO. 3
ADDRESS
OE
CE
WE
UB, LB
OUT
D
D
IN
(WE Controlled. OE is LOW During Write Cycle)
t
WC
VALID ADDRESS
LOW
LOW
t
AW
t
PWE2
t
SA
DATA UNDEFINED
t
HZWE
t
PBW
HIGH-Z
t
SD
DATAIN VALID
(1)
7
8
t
HA
9
10
11
t
LZWE
t
HD
UB_CEWR3.eps
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
9
IS61LV25616 ISSI
AC WAVEFORMS
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write)
t
WC
(1,3)
t
WC
®
ADDRESS
OE
CE
WE
UB, LB
OUT
D
D
IN
LOW
t
HZWE
DATA UNDEFINED
ADDRESS 1 ADDRESS 2
t
SA
t
HA
t
SA
t
t
SD
PBW
WORD 1
HIGH-Z
DATA
VALID
t
HD
IN
t
SD
t
PBW
WORD 2
DATA
VALID
t
HA
t
LZWE
t
HD
IN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The
t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
IS61LV25616 ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
®
Speed Order Part No. Package
(ns)
7 IS61LV25616-7T TSOP (Type II)
IS61LV25616-7K 400-mil SOJ
IS61LV25616-7LQ LQFP
IS61LV25616-7B Mini BGA
8 IS61LV25616-8T TSOP (Type II)
IS61LV25616-8K 400-mil SOJ
IS61LV25616-8LQ LQFP
IS61LV25616-8B Mini BGA
10 IS61LV25616-10T TSOP (Type II)
IS61LV25616-10K 400-mil SOJ
IS61LV25616-10LQ LQFP
IS61LV25616-10B Mini BGA
12 IS61LV25616-12T TSOP (Type II)
IS61LV25616-12K 400-mil SOJ
IS61LV25616-12LQ LQFP
IS61LV25616-12B Mini BGA
15 IS61LV25616-15T TSOP (Type II)
IS61LV25616-15K 400-mil SOJ
IS61LV25616-15LQ LQFP
IS61LV25616-15B Mini BGA
(8mm x 10mm)
(8mm x 10mm)
(8mm x 10mm)
(8mm x 10mm)
(8mm x 10mm)
Speed Order Part No. Package
(ns)
8 IS61LV25616-8TI TSOP (Type II)
IS61LV25616-8KI 400-mil SOJ
IS61LV25616-8LQI LQFP
IS61LV25616-8BI Mini BGA
10 IS61LV25616-10TI TSOP (Type II)
IS61LV25616-10KI 400-mil SOJ
IS61LV25616-10LQI LQFP
IS61LV25616-10BI Mini BGA
12 IS61LV25616-12TI TSOP (Type II)
IS61LV25616-12KI 400-mil SOJ
IS61LV25616-12LQI LQFP
IS61LV25616-12BI Mini BGA
15 IS61LV25616-15TI TSOP (Type II)
IS61LV25616-15KI 400-mil SOJ
IS61LV25616-15LQI LQFP
IS61LV25616-15BI Mini BGA
Shaded area product in development
1
2
(8mm x 10mm)
3
(8mm x 10mm)
4
(8mm x 10mm)
5
(8mm x 10mm)
6
Shaded area product in development
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/29/00
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