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IS61LV256
IS61LV256
ISSI
ISS I
32K x 8 LOW VOLT AGE CMOS STA TIC RAM FEBRUARY 1996
®
®
FEATURES
• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 345 mW (max.) operating
— 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields
access times as fast as 12 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil DIP and SOJ, plus the 450-mil TSOP package.
A0-A14
VCC
GND
I/O0-I/O7
CE
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-1
Page 2
ISS I
®
IS61LV256
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CONFIGURATION
28-Pin DIP and SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTIONS
PIN CONFIGURATION
28-Pin TSOP
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
TRUTH TABLE
A0-A14 Address Inputs
CE
OE
WE
Chip Enable Input
Output Enable Input
Write Enable Input
I/O0-I/O7 Input/Output
Mode
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
WEWE
WE
WEWE
Vcc Power
GND Ground
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2-2
CECE
CE
CECE
OEOE
OE
I/O Operation Vcc Current
OEOE
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
Page 3
IS61LV256
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage V CC = Min., IOH = –2.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –2 2 µA
(1)
–0.3 0.8 V
Ind. –5 5
Ind. –5 5
®
ISS I
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-12 ns -15 ns -20 ns -25 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC1 Vcc Operating VCC = Max., CE = VIL Com. — 50 — 50 — 50 — 50 mA
Supply Current IOUT = 0 mA, f = 0 Ind. — — — 60 — 60 — 60
ICC2 Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 100 — 90 — 80 — 70 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 100 — 90 — 80
ISB1 TTL Standby Current VCC = Max., Com. — 10 — 10 — 10 — 10 mA
(TTL Inputs) VIN = VIH or VIL Ind. — — — 20 — 20 — 20
CE
≥ VIH, f = 0
ISB2 CMOS Standby VCC = Max., Com. — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs)CE ≤ VCC – 0.2V, Ind. — — — 5 — 5 — 5
VIN > VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = f
CAPACITANCE
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-3
Page 4
ISS I
®
IS61LV256
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-12 ns -15 ns -20 ns -25 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 12 — 15 — 20 — 25 — ns
tAA Address Access Time — 12 — 15 — 20 — 25 ns
tOHA Output Hold Time 2 — 2 — 2 — 2 — ns
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
CE
Access Time — 12 — 15 — 20 — 25 ns
OE
Access Time — 6 — 7 — 8 — 9 ns
(2)
OE
to Low-Z Output 0 — 0 — 0 — 0 — ns
(2)
OE
to High-Z Output — 7 — 8 — 9 — 10 ns
(2)
CE
to Low-Z Output 3 — 3 — 3 — 3 — ns
(2)
CE
to High-Z Output — 5 — 6 — 9 — 10 ns
(3)
CE
to Power-Up 0 — 0 — 0 — 0 — ns
(3)
CE
to Power-Down — 13 — 15 — 18 — 20 ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1a and 1b
AC TEST LOADS
635 Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
702 Ω
3.3V
OUTPUT
5 pF
Including
jig and
scope
635 Ω
702 Ω
2-4
Figure 1a. Figure 1b.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
Page 5
IS61LV256
AC WAVEFORMS
®
ISS I
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
(1,3)
t
RC
t
AA
t
OHA
DATA VALID
t
RC
t
AA
t
t
OHA
OHA
t
DOE
t
LZOE
D
CE
OUT
HIGH-Z
t
PU
t
LZCE
t
ACE
SUPPLY
CURRENT
Notes:
1.WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL.
3. Address is valid prior to or coincident with CE LOW transitions.
t
HZCE
DATA VALID
t
HZOE
t
PD
ICC
50%50%
ISB
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-5
Page 6
ISS I
®
IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-12 ns -15 ns -20 ns -25 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 12 — 15 — 20 — 25 — ns
tSCE
CE
to Write End 8 — 10 — 13 — 15 — ns
tAW Address Setup Time to Write End 8 — 10 — 15 — 20 — ns
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
(4)
tPWE
WE
Pulse Width 8 — 10 — 13 — 15 — ns
tSD Data Setup to Write End 6 — 8 — 10 — 12 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
WE
LOW to High-Z Output — 6 — 7 — 8 — 10 ns
(2)
WE
HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1 (
ADDRESS
CE
WE
OUT
D
D
IN
WEWE
WE
Controlled)
WEWE
t
SA
DATA UNDEFINED
(1,2)
t
AW
t
HZWE
t
SCE
t
WC
t
PWE
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
LZWE
t
HD
2-6
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
Page 7
IS61LV256
®
ISS I
WRITE CYCLE NO. 2 (
CECE
CE
Controlled)
CECE
(1,2)
t
WC
ADDRESS
t
SA
t
SCE
t
HA
CE
t
AW
t
PWE
WE
t
HZWE
D
OUT
D
IN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ V
DATA UNDEFINED
IH.
HIGH-Z
t
SD
DATA-IN VALID
t
LZWE
t
HD
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
12 IS61LV256-12N 300-mil Plastic DIP
12 IS61LV256-12T TSOP - 450 mil
12 IS61LV256-12J 300-mil Plastic SOJ
15 IS61LV256-15N 300-mil Plastic DIP
15 IS61LV256-15T 450-mil TSOP
15 IS61LV256-15J 300-mil Plastic SOJ
20 IS61LV256-20N 300-mil Plastic DIP
20 IS61LV256-20T 450-mil TSOP
20 IS61LV256-20J 300-mil Plastic SOJ
25 IS61LV256-25N 300-mil Plastic DIP
25 IS61LV256-25T 450-mil TSOP
25 IS61LV256-25J 300-mil Plastic SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
12 IS61LV256-12NI 300-mil Plastic DIP
12 IS61LV256-12TI TSOP - 450 mil
12 IS61LV256-12JI 300-mil Plastic SOJ
15 IS61LV256-15NI 300-mil Plastic DIP
15 IS61LV256-15TI 450-mil TSOP
15 IS61LV256-15JI 300-mil Plastic SOJ
20 IS61LV256-20NI 300-mil Plastic DIP
20 IS61LV256-20TI 450-mil TSOP
20 IS61LV256-20JI 300-mil Plastic SOJ
25 IS61LV256-25NI 300-mil Plastic DIP
25 IS61LV256-25TI 450-mil TSOP
25 IS61LV256-25JI 300-mil Plastic SOJ
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-7
Page 8
ISS I
®
IS61LV256
2-8
®
I SSI
Integrated Silicon Solution, Inc.
680 Almanor Avenue
Sunnyvale, CA 94086
Fax: (408) 245-4774
Toll Free: 1-800-379-4774
http://www.issiusa.com
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
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