Datasheet IS61LV12824-8B, IS61LV12824-12B, IS61LV12824-9B, IS61LV12824-10B Datasheet (ICSI)

FEATURES

• High-speed access time: 8, 9, 10, 12 ns

• CMOS low power operation

— 720 mW (typical) operating @ 9 ns
— 36 mW (typical) standby @ 9 ns

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Available in 119-pin 14x22mm PBGA

DESCRIPTION

The ICSI IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using ICSI's high­performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac­cess times as fast as 8 ns with low power consumption.

When CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa­tion can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE1, CE2, CE2 and OE. The active
LOW Write Enable (WE) controls both writing and reading of
the memory.

The IS61LV12824 is packaged in the JEDEC standard
119-pin 14*22mm PBGA.

FUNCTIONAL BLOCK DIAGRAM

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

A0-A16

CE1

OE
WE

128K x 24

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

CE2

CE2

I/O0-I/O23

IS61LV12824

128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

Integrated Circuit Solution Inc. 1

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IS61LV12824

128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

IS61LV12824

2 Integrated Circuit Solution Inc.

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PIN DESCRIPTIONS

A0-A16 Address Inputs

I/O0-I/O23 Data Inputs/Outputs
CE1, CE2 Chip Enable Input LOW

CE2 Chip Enable Input HIGH

OE Output Enable Input
WE Write Enable Input

NC No Connection

Vcc Power

VCCQ I/O Power

GND Ground

PIN CONFIGURATION
119-pin 14x22mm PBGA

1234567

A NC A11 A14 A15 A16 A4 NC
B NC A12 A13 CE1 A5 A3 NC
C I/O16 NC CE2 NC CE2 NC I/O0

D I/O17 VCCQ GND GND GND VCCQ I/O1

E I/O18 GND VCC GND VCC GND I/O2

F I/O19 VCCQ GND GND GND VCCQ I/O3

G I/O20 GND VCC GND VCC GND I/O4

H I/O21 VCCQ GND GND GND VCCQ I/O5

J VCCQ GND VCC GND VCC GND VCCQ

K I/O22 VCCQ GND GND GND VCCQ I/O6

L I/O23 GND VCC GND VCC GND I/O7

M I/O12 VCCQ GND GND GND VCCQ I/O8

N I/O13 GND VCC GND VCC GND I/O9

P I/O14 VCCQ GND GND GND VCCQ I/O10

R I/O15NCNCNCNCNCI/O11
T NC A10 A8 WE A0 A1 NC
U NC A9 A7 OE A6 A2 NC

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OPERATING RANGE

Range Ambient Temperature VCC (8, 9, 10 ns) VCC (12 ns)

Commercial 0°C to +70°C 3.3V + 10%, – 5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V + 10%, – 5% 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

VIH Input HIGH Voltage 2.2 VCC + 0.3 V

VIL Input LOW Voltage

(1)

–0.3 0.8 V

ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –1 1 µA

Note:

1. V

IL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns).

VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns).

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VCC Power Supply Voltage Relative to GND –0.5 to 5.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to + 150 °C
TBIAS Temperature Under Bias: Com. –10 to + 85 °C

Ind. –45 to + 90 °C
PT Power Dissipation 2.0 W
IOUT DC Output Current ±20 mA

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

Mode

WEWE

WEWE

WE

CE1CE1

CE1CE1

CE1 CE2

CE2CE2

CE2CE2

CE2

OEOE

OEOE

OE I/O0-I/O23 Vcc Current

Not Selected X H X X X High-Z ISB1, ISB2
Output Disabled H L H L H High-Z ICC

X L H L X High-Z

Read H L H L L DOUT 1CC

H L H L H High-Z

Write L L H L X D

IN ICC

LLHLH HIHG-Z

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CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -9 ns -10 ns -12 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., Com. — 210 — 200 — 180 — 190 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — — — 220 — 210 — 190

I

SB1 TTL Standby Current VCC = Max., Com. — 70 — 60 — 50 — 50 mA

(TTL Inputs) VIN = VIH or VIL, f = 0 Ind. — 70 — 70 — 55 — 55

CE1, CE2, ≥ VIH, CE2 ≤ VIL

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA

Current (CMOS Inputs) CE1, CE2 ≥ VCC – 0.2V, Ind. — — — 20 — 20 — 20

CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, f = 0

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 2 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1 and 2

AC TEST LOADS

Figure 1 Figure 2

319 Ω

5 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

OUTPUT

Z

O

= 50Ω

1.5V

50Ω

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READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 -9 -10 -12

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 9 — 10 — 12 — 15 — ns

tAA Address Access Time — 9 — 10 — 12 — 15 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE1, CE2 Access Time — 8 — 9 — 10 — 12 ns

tACE2 CE2 Access Time
tDOE OE Access Time — 4 — 4 — 4 — 4 ns

tHZOE

(2)

OE to High-Z Output 0 5 0 5 0 6 0 7 ns

tLZOE

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

tHZCE

(2)

CE1, CE2 to High-Z Output 0 5 0 5 0 6 0 7 ns

tHZCE

2

(2)

CE2 to High-Z Output

tLZCE

(2)

CE, CE2 to Low-Z Output 3 — 3 — 3 — 3 — ns

tLZCE

2

(2)

CE2 to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

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READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH)

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1, CE2 = V

IL. CE2 = VIH.

3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition.

DATA VALID

PREVIOUS DATA VALID

t

AA

t

OHA

t

OHA

t

RC

D

OUT

ADDRESS

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACE1

t

ACE2

t

LZCE1

t

LZCE2

t

HZOE

HIGH-Z

DATA VALID

ADDRESS

OE

CE1, CE2

CE2

D

OUT

t

HZCE1

t

HZCE2

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WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 -9 -10 -12

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 8 — 9 — 10 — 12 — ns
tSCE CE1, CE2 to Write End 7 — 8 — 8 — 9 — ns

tSCE

2

CE2 to Write End 7 — 8 — 8 — 9 —

tAW Address Setup Time 7 — 8 — 8 — 9 — ns

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE1 WE Pulse Width (OE = HIGH) 6 — 8 — 8 — 9 — ns
tPWE2 WE Pulse Width (OE = LOW) 6 — 9 — 9 — 10 — ns

tSD Data Setup to Write End 4.5 — 5 — 5 — 5 — ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

tHZWE

(2)

WE LOW to High-Z Output — 3.5 — 3.5 — 3.5 — 3.5 ns

tLZWE

(2)

WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns

Notes:

1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.

WRITE CYCLE NO. 1

(WE Controlled)

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCE1

t

SCE2

t

PWE1

t

PWE2

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE1, CE2

CE2

WE

D

OUT

D

IN

DATAIN VALID

t

LZWE

t

SD

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WRITE CYCLE NO. 2

(1)

(CE Controlled: OE = HIGH or LOW: CE1, CE2 or CE2 Terminates Write)

DATA UNDEFINED

LOW

t

WC

VALID ADDRESS

t

PWE1

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE1, CE2

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

HIGH

CE2

WRITE CYCLE NO. 2

(1)

(WE Controlled: OE = LOW, CE1, CE2 = LOW; CE2 = HIGH: WE T

EMINATES WRITE

)

Note:

1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.

DATA UNDEFINED

t

WC

VALID ADDRESS

LOW

LOW

t

PWE2

t

AW

t

HA

HIGH-Z

t

HD

t

SA

t

HZWE

ADDRESS

CE1, CE2

WE

D

OUT

D

IN

OE

DATAIN VALID

t

LZWE

t

SD

HIGH

CE2

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ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IS61LV12824-8B 14*22mm PBGA

9 IS61LV12824-9B 14*22mm PBGA

10 IS61LV12824-10B 14*22mm PBGA

12 IS61LV12824-12B 14*22mm PBGA

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: [phone]

Fax: [phone]

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: [phone]

FAX: [phone]

http://www.icsi.com.tw

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