Datasheet IS61LV12816-10KI, IS61LV12816-10BI, IS61LV12816-10B, IS61LV12816-8K, IS61LV12816-8BI Datasheet (ISSI)

IS61LV12816 ISSI

128K x 16 HIGH-SPEED CMOS STATIC RAM

®

WITH 3.3V SUPPLY

FEATURES

• High-speed access time: 8, 10, 12, and 15 ns

• CMOS low power operation

• TTL and CMOS compatible interface levels

• Single 3.3V ± 10% power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

FUNCTIONAL BLOCK DIAGRAM

NOVEMBER 2000

DESCRIPTION

The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IS61LV12816 is packaged in the JEDEC standard 44-pin
400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini
BGA (6mm x 8mm).

A0-A16

VCC

GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE

OE
WE

UB

LB

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

128K x 16

MEMORY ARRAY

COLUMN I/O

Integrated Silicon Solution, Inc. — 1-800-379-4774

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

Rev. A

11/30/00

11/30/00

1

1

IS61LV12816

PIN CONFIGURATIONS

44-Pin SOJ (K)

A4

A3

A2

A1

A0

CE

I/O0

I/O1

I/O2

I/O3

Vcc

GND

I/O4

I/O5

I/O6

I/O7

WE

A16

A15

A14

A13

A12

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

A6

A7

OE

UB

LB

I/O15

I/O14

I/O13

I/O12

GND

Vcc

I/O11

I/O10

I/O9

I/O8

NC

A8

A9

A10

A11

NC

44-Pin TSOP (T)

A4
A3
A2
A1
A0

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE
A16
A15
A14
A13
A12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

ISSI

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O15

37

I/O14

36

I/O13

35

I/O12

34

GND

33

Vcc

32

I/O11

31

I/O10

30

I/O9

29

I/O8

28

NC

27

A8

26

A9

25

A10

24

A11

23

NC

®

48-Pin mini BGA (B)

1 2 3 4 5 6

LB

I/O

I/O

GND

Vcc

I/O

I/O

NC

8

9

14

15

OE

UB A3

I/O10A5

I/O

11

I/O12NC

I/O

13

NC

A8

A

B

C

D

E

F

G

H

2

A14

A12

44-Pin LQFP (LQ)

A16

A15

A14

A13

A12

A11

A10A9OEUBLB

44 43 42 41 40 39 38 37 36 35 345

CE

A1

A0

NC

A9

A16

A15

A13

A10

A4

A6

A7

A2

CE I/O

I/O1I/O

I/O

3

I/O

GND

4

I/O

I/O

5

WE

A11 NC

N/C

I/O

0

2

Vcc

6

7

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

1
2
3
4
5
6

TOP VIEW

7
8
9
10
11

12 13 14 15 16 17 18 19 20 21 22

A0A1A2A3A4NCA5A6A7

WE

Integrated Silicon Solution, Inc. — 1-800-379-4774

33
32
31
30
29
28
27
26
25
24
23

A8

I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC

Rev. A

11/30/00

IS61LV12816

®

ISSI

PIN DESCRIPTIONS

A0-A16 Address Inputs

I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection

Vcc Power

GND Ground

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC Power Supply Voltage Relative to GND –0.5 to 5.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to + 150 °C
TBIAS Temperature Under Bias: Com. –10 to + 85 °C

PT Power Dissipation 2.0 W
IOUT DC Output Current ±20 mA

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

(1)

Ind. –45 to + 90 °C

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to + 70°C 3.3V ± 10%
Industrial –40°C to + 85°C 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

(1)

(1)

2VCC + 0.3 V

–0.3 0.8 V

3

VIH Input HIGH Voltage

VIL Input LOW Voltage

ILI Input Leakage GND - VIN - VCC –11µA

ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –11µA

Note:

IL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).

1. V

IH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).

V

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

IS61LV12816

ISSI

TRUTH TABLE

I/O PIN

Mode WE CE OE LB U B I/O0-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

®

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Operating VCC = Max., CE = VIL Com. — 150 — 125 — 110 — 90 mA

Supply Current IOUT = 0 mA, f = Max. Ind. — 160 — 135 — 120 — 100

ISB1 TTL Standby VCC = Max., Com. — 50 — 40 — 35 — 30 mA

Current VIN = VIH or VIL Ind. — 60 — 50 — 45 — 40
(TTL Inputs) CE • VIH, f = max

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA

Current CE - VCC – 0.2V, Ind. — 20 — 20 — 20 — 20
(CMOS Inputs) VIN > VCC – 0.2V, or

VIN - 0.2V, f = 0

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

IS61LV12816

®

ISSI

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 8 — 10 — 12 — 15 — ns

tAA Address Access Time — 8 — 10 — 12 — 15 ns

tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time 8 ——10 — 12 — 15 ns
tDOE OE Access Time — 3 — 4 — 5 — 6ns

(2)

tHZOE

tLZOE

tHZCE

tLZCE

OE to High-Z Output — 3 — 4 — 506ns

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

(2)

CE to High-Z Output 0 3 0 4 0 5 0 8 ns

(2)

CE to Low-Z Output 3 — 3 — 3 — 3 — ns

tBA LB, UB Access Time — 3 — 4 — 5 — 6ns

(2)

tHZB

tLZB

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

LB, UB to High-Z Output 0 3 0 4 0 5 0 6 ns

(2)

LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns

of 0V to 3.0V and output loading specified in Figure 1.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1 and 2

AC TEST LOADS

3.3V

OUTPUT

30 pF

Including

jig and

scope

319 Ω

3.3V

OUTPUT

353 Ω

5 pF

Including

jig and

scope

319 Ω

353 Ω

Figure 1.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

Figure 2.

5

IS61LV12816

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

t

OHA

®

ISSI

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

CE

t

LZCE

LB, UB

D

OUT

HIGH-Z

PREVIOUS DATA VALID

(1,3)

t

AA

t

DOE

t

LZB

t

LZOE

t

ACE

t

BA

DATA VALID

READ1.eps

t

RC

t

OHA

t

HZOE

t

HZCE

t

HZB

DATA VALID

UB_CEDR2.eps

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transition.

6

IL.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

IS61LV12816

®

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

-8 ns -10 ns -12 ns -15 ns

Symbol Parameter Min. Max Min. Max. Min. Max. Min. Max. Unit

(1,3)

(Over Operating Range)

tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 6.5 — 8 — 8 — 10 — ns

tAW Address Setup Time 6.5 — 8 — 8 — 10 — ns

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns

tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 6.5 — 8 — 9 — 10 — ns
tPWE1 WE Pulse Width (OE = HIGH) 5 — 7 — 8 — 10 — ns
tPWE2 WE Pulse Width (OE = LOW) 6.5 — 8 — 10 — 11 — ns

tSD Data Setup to Write End 4 — 5 — 6 — 7 — ns

tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

(3)

tHZWE

tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V

2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

WE LOW to High-Z Output — 3 — 4 — 5 — 6ns

(3)

WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns

to 3.0V and output loading specified in Figure 1.

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

7

IS61LV12816

®

ISSI

WRITE CYCLE NO. 1

ADDRESS

CE

WE

UB, LB

D

OUT

DATA UNDEFINED

(1,2)

(CE Controlled, OE = HIGH or LOW)

VALID ADDRESS

t

SA

t

AW

t

PWE1

t

PWE2

t

HZWE

t

WC

t

SCE

t

PBW

HIGH-Z

t

SD

t

t

HD

t

HA

LZWE

D

IN

DATAIN VALID

UB_CEWR1.eps

8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

IS61LV12816

WRITE CYCLE NO. 2

(1)

(WE Controlled, OE = HIGH during Write Cycle)

t

WC

®

ISSI

ADDRESS

VALID ADDRESS

OE

LOW

CE

t

AW

t

PWE1

WE

t

SA

t

PBW

UB, LB

t

HZWE

D

OUT

D

DATA UNDEFINED

IN

HIGH-Z

t

SD

DATAIN VALID

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

t

HA

t

LZWE

t

HD

UB_CEWR2.eps

ADDRESS

OE

CE

WE

UB, LB

D

OUT

D

IN

LOW

LOW

t

SA

DATA UNDEFINED

t

WC

VALID ADDRESS

t

AW

t

PWE2

t

t

HZWE

PBW

HIGH-Z

t

SD

DATAIN VALID

t

HA

t

LZWE

t

HD

UB_CEWR3.eps

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

9

IS61LV12816

®

ISSI

WRITE CYCLE NO. 4

ADDRESS

OE

CE

LOW

WE

UB, LB

D

OUT

D

DATA UNDEFINED

IN

(LB, UB Controlled, Back-to-Back Write)

t WC

ADDRESS 1 ADDRESS 2

t SA

t HA t HA

t SA

t PBW

WORD 1

t HZWE

HIGH-Z

t HD

t SD

DATA

IN

VALID

t WC

t SD

(1,3)

t PBW

WORD 2

DATA

VALID

t LZWE

t HD

IN

UB_CEWR4.eps

Notes:

1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

t SA, t HA, t SD, and t HD timing is

10

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

IS61LV12816

®

ISSI

IS61LV12816 STANDARD VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IS61LV12816-8B mini BGA

IS61LV12816-8K 400-mil Plastic SOJ
IS61LV12816-8LQ LQFP
IS61LV12816-8T Plastic TSOP

10 IS61LV12816-10B mini BGA

IS61LV12816-10K 400-mil Plastic SOJ
IS61LV12816-10LQ LQFP
IS61LV12816-10T Plastic TSOP

12 IS61LV12816-12B mini BGA

IS61LV12816-12K 400-mil Plastic SOJ
IS61LV12816-12LQ LQFP
IS61LV12816-12T Plastic TSOP

15 IS61LV12816-15B mini BGA

IS61LV12816-15K 400-mil Plastic SOJ
IS61LV12816-15LQ LQFP
IS61LV12816-15T Plastic TSOP

(6mm x 8mm)

(6mm x 8mm)

(6mm x 8mm)

(6mm x 8mm)

IS61LV12816 STANDARD VERSION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

8 IS61LV12816-8BI mini BGA

IS61LV12816-8KI 400-mil Plastic SOJ
IS61LV12816-8LQI LQFP
IS61LV12816-8TI Plastic TSOP

10 IS61LV12816-10BI mini BGA

IS61LV12816-10KI 400-mil Plastic SOJ
IS61LV12816-10LQI LQFP
IS61LV12816-10TI Plastic TSOP

12 IS61LV12816-12BI mini BGA

IS61LV12816-12KI 400-mil Plastic SOJ
IS61LV12816-12LQI LQFP
IS61LV12816-12TI Plastic TSOP

15 IS61LV12816-15BI mini BGA

IS61LV12816-15KI 400-mil Plastic SOJ
IS61LV12816-15LQI LQFP
IS61LV12816-15TI Plastic TSOP

(6mm x 8mm)

(6mm x 8mm)

(6mm x 8mm)

(6mm x 8mm)

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/30/00

®

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: [phone]
Fax: [phone]

E-mail: [e-mail]

www.issi.com

11