Page 1
查询42S16800A供应商
IS42S81600A,
IS42S16800A,
IS42S32400A,
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166,143,100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
DD VDDQ
V
IS42S81600A 3.3V 3.3V
IS42S16800A 3.3V 3.3V
IS42S32400A 3.3V 3.3V
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600A IS42S16800A IS42S32400A
4M x8x4 Banks 2M x16x4 Banks 1M x32x4 Banks
54-pin TSOPII 54-pin TSOPII 86-pin TSOPII
®
ISSI
PRELIMINARY INFORMATION
JANUARY 2005
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
KEY TIMING PARAMETERS
Parameter -6 -7 -10 Unit
Clk Cycle Time
CAS Latency = 3 6 7 10 ns
CAS Latency = 2 - 10 10 ns
Clk Frequency
CAS Latency = 3 166 143 100 M h z
CAS Latency = 2 - 100 100 M hz
Access Time from Clock
CAS Latency = 3 5.4 5.4 7 ns
CAS Latency = 2 - 6 9 ns
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION, Rev. 00C
01/20/05
1-800-379-4774
1
Page 2
IS42S81600A, IS42S16800A, IS42S32400A
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function enabled.
Precharge
one bank while accessing one of the
other three banks will hide the
seamless, high-speed, random-access operation.
SDRAM
a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
®
ISSI
precharge
read and write accesses are burst oriented starting at
cycles and provide
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
ADDRESS
LATCH
12
ROW
ADDRESS LATCH
9
BURST COUNTER
ADDRESS BUFFER
MODE
REGISTER
COLUMN
COLUMN
REFRESH
CONTROLLER
12
MULTIPLEXER
REFRESH
CONTROLLER
REFRESH
COUNTER
ADDRESS
BUFFER
12
SELF
ROW
12
ROW DECODER
BANK CONTROL LOGIC
DATA IN
BUFFER
16
DATA OUT
BUFFER
16 16
4096
4096
4096
4096
MEMORY CELL
SENSE AMP I/O GATE
512
(x 16)
COLUMN DECODER
9
16
2
ARRAY
BANK 0
DQML
DQMH
I/O 0-15
V
DD/VDDQ
Vss/V
ss
Q
2
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 3
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
®
ISSI
I/O0
V
DD
I/O1
V
SS
I/O2
V
DD
I/O3
V
SS
CAS
RAS
BA0
BA1
V
DD
NC
NC
NC
NC
V
DD
NC
WE
CS
A10
A0
A1
A2
A3
V
DD
1
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O7
V
SS
NC
I/O6
V
DD
NC
I/O5
V
SS
NC
I/O4
V
DD
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Q
Q
Q
Q
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A9 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O7 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
WE Write Enable
DQ M x 8 Lower Byte, Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
3
Page 4
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
®
ISSI
V
DD
I/O0
V
DD
I/O1
I/O2
V
SS
I/O3
I/O4
V
DD
I/O5
I/O6
SS
V
I/O7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O15
V
SS
Q
I/O14
I/O13
V
DD
Q
I/O12
I/O11
V
SS
Q
I/O10
I/O9
DD
Q
V
I/O8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A8 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O15 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
4
Integrated Silicon Solution, Inc. — www.issi.com —
WE Write Enable
DQML x16 Lower Byte, Input/Output Mask
DQMH x16 Upper Byte, Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05
Page 5
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
1
NC
CS
NC
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
DD
16
17
18
19
20
21
22
23
24
25
A0
26
A1
27
A2
28
29
DD
30
31
32
Q
33
34
35
Q
36
37
38
Q
39
40
41
Q
42
43
DD
I/O0
V
DD
I/O1
I/O2
V
SS
I/O3
I/O4
DD
V
I/O5
I/O6
V
SS
I/O7
V
DQM0
CAS
RAS
A11
BA0
BA1
A10
DQM2
V
I/O16
V
SS
I/O17
I/O18
V
DD
I/O19
I/O20
V
SS
I/O21
I/O22
V
DD
I/O23
V
WE
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
I/O15
V
SS
I/O14
I/O13
V
DD
I/O12
I/O11
SS
V
I/O10
I/O9
V
DD
I/O8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
I/O31
V
DD
I/O30
I/O29
V
SS
I/O28
I/O27
V
DD
I/O26
I/O25
V
SS
I/O24
V
SS
®
ISSI
Q
Q
Q
Q
Q
Q
Q
Q
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A7 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O31 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
WE Write Enable
DQM0-DQM3 x32 Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
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Page 6
IS42S81600A, IS42S16800A, IS42S32400A
PIN FUNCTIONS
Symbol Type Function (In Detail)
®
ISSI
A0-A11
BA0, BA1 Input Pin
CAS
CKE
CLK
CS
DQML,
DQMH mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A9 (x8); A0-A8
(x16); A0-A7(x32) with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode.
CKE is an asynchronous i
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. WhenDQML or DQMH is HIGH, input data is masked and
cannot be written to the device.
nput.
DQM0-DQM3
DQ M Input Pin For IS42S81600A only.
RAS
WE
VDDQ
VDD
VSSQ
VSS
6
Input Pin For IS42S32400A only
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSS is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 7
IS42S81600A, IS42S16800A, IS42S32400A
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A9 (x8); A0-A8 (x16); A0-A7 (x32) provides the
starting column location. When A10 is HIGH, this command
functions as an AUTO PRECHARGE command. When the
auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst. The row will
remain open for subsequent accesses when AUTO
PRECHARGE is not selected. DQ’s read data is subject to
the logic level on the DQM inputs two clocks earlier. When
a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide
valid data when the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A9
(x8); A0-A8 (x16); A0-A7 (x32). Whether or not AUTOPRECHARGE is used is determined by A10.
The row being accessed will be precharged at the end of the
WRITE burst, if AUTO PRECHARGE is selected. If AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
A memory array is written with corresponding input data on
DQ’s and DQM input logic level appearing at the same time.
Data will be written to memory when DQM signal is LOW.
When DQM is HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. BA0,
BA1 can be used to select which bank is precharged or they
are treated as “Don’t Care”. A10 determined whether one or
all banks are precharged. After executing this command,
the next command for the selected banks(s) is executed
after passage of the period tRP, which is the period required
for bank precharging. Once a bank has been precharged,
it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge
is initiated at the earliest valid stage within a burst. This
function allows for individual-bank precharge without requiring an explicit command. A10 to enable the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE burst,
a precharge of the bank/row that is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC) is
required for a single refresh operation, and no other commands can be executed during this period. This command is
executed at least 4096 times for every 64ms. During an
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates the
burst read and write operations by truncating either fixedlength or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only be
issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
®
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
7
Page 8
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
COMMAND TRUTH TABLE
CKE A11
Function Symbol n – 1 n
Device deselect H × H × × × × × × ×
No operation H × L H H H × × ×
Burst stop H H L H H L × × × ×
Read H × L H L H V V L V
Read with auto precharge H × L H L H V V H V
Write H × L H L L V V L V
Write with auto precharge H × L H L L V V H V
Bank activate H × L L H H V V V V
Precharge select bank H × L L H L V V L ×
Precharge all banks H × L L H L × × H ×
Mode register set H × L L L L L L L V
CSCS
CS
CSCS
RASRAS
RAS
RASRAS
CASCAS
CAS
CASCAS
WEWE
WE B A1 BA 0 A1 0 A9 - A0
WEWE
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
DQM TRUTH TABLE
CKE DQM
Function Symbol n- 1 n U L
Data write / output enable H × L L
Data mask / output disable H × H H
Upper byte write enable / output enable H × L ×
Lower byte write enable / output enable H × × L
Upper byte write inhibit / output disable H × H ×
Lower byte write inhibit / output disable H × × H
Note: H=V
IH, L=VIL x= VIH or VIL, V = Valid Data.
8
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 9
IS42S81600A, IS42S16800A, IS42S32400A
CKE TRUTH TABLE
CKE
Current State /Function n – 1 n CS RAS CAS WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend mode exit L H × × × × ×
Auto refresh command Idle H H L L L H ×
Self refresh entry Idle H L L L L H ×
Power down entry Idle H L L H H H ×
HL H × ×× ×
Deep power down entry H L L H H L ×
Self refresh exit L H L H H H ×
LH H× ×× ×
Power down exit L H L H H H ×
LH H× ×× ×
Deep power down exit L H × × × × ×
®
ISSI
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
9
Page 10
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE
CSCS
RAS RAS
CASCAS
CS
RAS
CSCS
RAS RAS
Idle H X X X X DESL Nop
LHHH X NOP Nop
LHHL X BST Nop
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L A, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT Row activating
L L H L BA, A10 PRE/PALL N op
L L L H X REF Auto refresh
L L L L OC, BA1=L MRS Mode register set
L L L L OC, BA1=H EMRS Extended mode register set
Row Active H X X X X DESL Nop
LHHH X NOP Nop
LHHL X BST Nop
L H L H BA, CA, A10 READ/READA Begin read
L H L L BA, CA, A10 WRIT/ WRITA Begin write
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Precharge/Precharge all banks
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Read H X X X X DESL Continue burst to end to
L H H H X NOP Continue burst to end Row
L H H L X BST Burst stop Row active
L H L H BA, CA, A10 READ/READA Terminate burst,
L H L L BA, CA, A10 WRIT/WRITA Terminate burst,
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Terminate burst
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write H X X X X DESL Continue burst to end
L H H H X NOP Continue burst to end
L H H L X BST Burst stop Row active
L H L H BA, CA, A10 READ/READA Terminate burst, start read :
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write :
L L H H BA, RA RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Terminate burst Precharging
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(2)
(2)
(3)
(3)
(2)
Row active
Row active
begin new read
begin write
(5, 6)
(2)
Precharging
Write recovering
Write recovering
Determine AP
Determine AP
(2)
(5)
(5, 6)
(5)
®
(
(7)
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
10
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 11
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CSCS
RAS RAS
CS
RAS
CSCS
RAS RAS
Read with auto H × × × × DESL Continue burst to end Precharging
Precharge L H H H x NOP Continue burst to end Precharging
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write with Auto H × × × × DESL Continue burst to end -Write
Precharge recovering with auto precharge
L H H H × NOP Continue burst to end -Write
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Precharging H × × × × DESL Nop Enter idle after tRP
L H H H × NOP Nop Enter idle after tRP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Nop Enter idle after tRP
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Row Activating H × × × × DESL Nop Enter bank active after tRCD
L H H H × NOP Nop Enter bank active after tRCD
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
CASCAS
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(2)
(2)
(2)
(2)
recoveringwith auto precharge
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2,8)
(2)
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
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IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CSCS
RAS RAS
CASCAS
CS
RAS
CSCS
RAS RAS
Write Recovering H × × × × DESL Nop Enter row active after tDPL
L H H H × NOP Nop Enter row active after tDPL
L H H L × BST Nop Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Begin read
L H L L BA, CA, A10 WRIT/ WRITA Begin new write
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write Recovering H × × × × DESL Nop Enter precharge after tDPL
with Auto L H H H × NOP Nop Enter precharge after tDPL
Precharge L H H L × BST Nop Enter row active after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × R EF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Refresh H × × × × DESL Enter idle after tRC1
L H H H × NOP Nop Enter idle after tRC1
L H H L × BST Nop Enter idle after tRC1
L H L H BA, CA, A10 EAD/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Mode Register H × × × × DESL Nop Enter idle after tRSC
Accessing L H H H × NOP Nop Enter idle after tRSC
L H H L × BST Nop Enter idle after tRSC
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(6)
(2)
(2)
(2, 6)
(2)
(2)
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
12
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PRELIMINARY INFORMATION Rev. 00C
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Page 13
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
3. Illegal if tRCD is not satisfied.
4. Illegal if tRAS is not satisfied.
5. Must satisfy burst interrupt condition.
6. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
7. Must mask preceding data which don’t satisfy tDPL.
8. Illegal if tRRD is not satisfied.
®
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13
Page 14
IS42S81600A, IS42S16800A, IS42S32400A
STATE DIAGRAM
Extended
Mode
Register
Set
SELF
Mode
Register
Set
EMRS
MRS
IDLE
SELF exit
REF
®
ISSI
Self
Refresh
CBR (Auto)
Refresh
WRITE
SUSPEND
WRITEA
SUSPEND
CKE
CKE
CKE
Write
Deep
Power
Down
WRITE
WRITEA
DPD
DPD Exit
BST
Write
Write with
RRE (Precharge term
ACT
Row
Active
Auto Precharge
Read
Auto Precharge
Write
ination)
CKE
CKE
CKE
CKE
BST
Read
Read with
READ
READA
PRE (Precharge termination)
Power
Down
Active
Power
Down
Read
CKE
CKECKE
CKE
CKE
READ
SUSPEND
READA
SUSPEND
14
POWER
ON
Precharge
Precharge
Automatic sequence
Manual Input
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Page 15
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VDD MAX Maximum Supply Voltage –0.5 to +4.6 V
VDDQ
MAX Maximum Supply Voltage for Output Buffer 0.5 to +4.6 V
VIN Input Voltage –0.5 to +4.6 V
VOUT Output Voltage –0.5 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature Com. 0 to +70 ° C
Ind. –40 to +85
TSTG Storage Temperature –55 to +125 °C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
DC RECOMMENDED OPERATING CONDITIONS
(2)
(At TA = 0 to +70°C)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 3.0 3.3 3.6 V
VDDQ I/O Supply Voltage 3.0 3.3 3.6 V
(1)
VIH
(2)
VIL
Note:
IH (max) = VDDQ +1.5V (PULSE WIDTH < 5NS).
1. V
2. VIL (min) = -1.5V (PULSE WIDTH < 5NS).
Input High Voltage 2.0 — VDDQ + 0.3 V
Input Low Voltage -0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ= 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter Typ. Max. Unit
CIN1 Input Capacitance: CLK — 3.5 pF
CIN2 Input Capacitance:All other input pins — 3.8 pF
CI/O Data Input/Output Capacitance:I/Os — 6.5 pF
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15
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IS42S81600A, IS42S16800A, IS42S32400A
ISSI
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
I
IL Input Leakage Current 0V ≤ VIN ≤ VCC, with pins other than –5 5 µA
the tested pin at 0V
IOL Output Leakage Current Output is disabled, 0V ≤ VOUT ≤ VCC –5 5 µA
VOH Output High Voltage Level IOUT = –2 mA 2. 4 — V
VOL Output Low Voltage Level IOUT = +2 mA — 0. 4 V
®
IDD1 Operating Current
IDD2P Precharge Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN)——3mA
IDD2PS (In Power-Down Mode) tCK = ∞ ——2mA
IDD2N Precharge Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN)——25mA
IDD2NS (In Non Power-Down Mode) tCK = ∞ ——15mA
IDD3P Active Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN)——10mA
IDD3PS (In Power-Down Mode) tCK = ∞ ——10mA
IDD3N Active Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN) Com. — — 35 mA
IDD3NS (In Non Power-Down Mode) tCK = ∞ Com. — — 30 mA
IDD4 Operating Current tCK = tCK (MIN) Com. -7 — 150 mA
(In Burst Mode)
IDD5 Auto-Refresh Current tRC = tRC (MIN) Com. -7 — 300 mA
IDD6 Self-Refresh Current CKE ≤ 0.2V Com. — — 2 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
DD1 and IDD4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
2. I
(1,2)
(1)
One Bank Operation, Com. -6 — 170 mA
Com. -7 — 160 mA
Burst Length=1 Ind. -7 — 170 m A
tRC ≥ tRC (min.) Com. -10 — 140 mA
IOUT = 0mA Ind. -10 — 150 m A
Ind. — — 45 mA
Ind. — — 35 mA
Com. -6 — 165 mA
IOUT = 0mA Ind. -7 — 160 mA
Com. -10 — 140 mA
Ind. -10 — 150 mA
Com. -6 — 330 mA
Ind. -7 — 330 mA
Com. -10 — 270 mA
Ind. -10 — 300 mA
Ind. — — 3 mA
DD and Vss for each memory
16
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Page 17
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6 -7 -10
Symbol Parameter Min. Max. Min. Max. Min. Max Units
CK3 Clock Cycle Time CAS Latency = 3 6 — 7 — 1 0 — n s
t
tCK2 CAS Latency = 2 — — 10 — 10 — ns
t
AC3 Access Time From CLK
(4)
CAS Latency = 3 — 5.4 — 5.4 — 7 ns
tAC2 CAS Latency = 2 — — — 6 — 9 ns
tCHI CLK HIGH Level Width 2.5 — 2.5 — 3.5 — n s
tCL CLK LOW Level Width 2.5 — 2.5 — 3.5 — ns
OH3 Output Data Hold Time CAS Latency = 3 2.5 — 2.5 — 2.5 — ns
t
tOH2 CAS Latency = 2 2.5 — 2.5 — 2.5 — ns
tLZ Output LOW Impedance Time 0 — 0 — 0 — ns
HZ3 Output HIGH Impedance Time
t
(5)
CAS Latency = 3 — 6 — 6 — 7 ns
tHZ2 CAS Latency = 2 — 6 — 6 — 9 n s
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1CLK+3
—
1CLK+3
—
1CLK+3
—ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
tDS Input Data Setup Time
tDH Input Data Hold Time
tAS Address Setup Time
tAH Address Hold Time
tCKS CKE Setup Time
tCKH CKE Hold Time
tCKA CKE to CLK Recovery Delay Time
tCS Command Setup Time (CS, RAS, CAS, WE, DQM)
tCH Command Hold Time (CS, RAS, CAS, WE, DQM)
tRC Command Period (REF to REF / ACT to ACT) 60 — 63 — 70 — n s
tRAS Command Period (ACT to PRE) 37
120,000
37
120,000
44
120,000
tRP Command Period (PRE to ACT) 18 — 18 — 20 — n s
tRCD Active Command To Read / Write Command Delay Time 1 8 — 18 — 20 — n s
tRRD Command Period (ACT [0] to ACT[1]) 12 — 14 — 15 — n s
tDPL3 Input Data To Precharge CAS Latency = 3 2CLK — 2CLK — 2CLK — ns
Command Delay time
tDPL2 CAS Latency = 2 2CLK — 2CLK — 2CLK — ns
tDAL3 Input Data To Active / Refresh CAS Latency = 3
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
Command Delay time (During Auto-Precharge)
tDAL2 CAS Latency = 2
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
tT Transition Time 0.5 30 0.5 30 0.5 30 ns
tREF Refresh Cycle Time (4096) — 64 — 64 — 64 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after V
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
3. Assumed input rise and fall time (t
considered and (t
4. Access time is measured at 1.5V with the load shown in the figure below.
5. The time t
when the output is in the high impedance state.
T = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
R & tF) = 1ns. If tR and tF are longer than 1ns, transient time compensation should be
R + tF) / 2-1 ns should be added to the parameter.
HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
DD and VDDQ reach their stipulated voltages.
ns
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IS42S81600A, IS42S16800A, IS42S32400A
ISSI
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER - 6 -7 -10. UNITS
— Clock Cycle Time 6 7 1 0 ns
— Operating Frequency 166 143 100 MHz
tCCD READ/WRITE command to READ/WRITE command 1 1 1 cycle
tCKED CKE to clock disable or power-down entry mode 1 1 1 cycle
tPED CKE to clock enable or power-down exit setup mode 1 1 1 cycle
tDQD DQM to input data delay 0 0 0 cycle
tDQM DQM to data mask during WRITEs 0 0 0 cycle
tDQZ DQM to data high-impedance during READs 2 2 2 cycle
tDWD WRITE command to input data delay 0 0 0 cycle
tDAL Data-in to ACTIVE command 5 4 4 cycle
tDPL Data-in to PRECHARGE command 2 2 2 cycle
tBDL Last data-in to burst STOP command 1 1 1 cycle
®
tCDL Last data-in to new READ/WRITE command 1 1 1 cycle
tRDL Last data-in to PRECHARGE command 2 2 2 cycle
tMRD LOAD MODE REGISTER command 2 2 2 cycle
to ACTIVE or REFRESH command
tROH Data-out to high-impedance from CL = 3 3 3 3 cycle
PRECHARGE command CL = 2 2 2 2
18
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Page 19
IS42S81600A, IS42S16800A, IS42S32400A
AC TEST CONDITIONS
Input Load Output Load
t
CK
CLK
INPUT
3.0V
1.5V
0V
3.0V
1.5V
0V
t
t
OH
CS
CHI
t
t
CH
t
AC
t
CL
Output
Z
= 50Ω
®
ISSI
1.5V
50Ω
30 pF
OUTPUT
1.5V 1.5V
AC TEST CONDITIONS
Parameter Unit
AC High Level Input Voltage/Low Level Input Voltage 3.0V to 0V
Input Rise and Fall Times 1 ns
Input Timing Reference Level 1.5V
Output Timing Measurement Reference Level 1.5V
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Page 20
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
FUNCTIONAL DESCRIPTION
The 128Mb SDRAMs are quad-bank DRAMs which operate at 2.5V or 3.3V and include a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CLK). Each of the 33,554,432-bit banks is organized
as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed
The address bits
tered coincident with the READ or WRITE command are
used to select the starting column location for the burst
access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
(BA0 and BA1 select the bank, A0-A11 select the row)
A0-A9 (x8); A0-A8 (x16); A0-A7 (X32)
regis-
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 128M SDRAM is initialized after the power is applied to
VDD and VDDQ (simultaneously) and the clock is stable.
A 200µs delay is required prior to issuing any command
other than a
INHIBIT or NOP may be applied during the 100us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All banks
.
must be precharged. This will leave all banks in an idle state
where two
the
AUTO REFRESH
ready for mode register programming.
The mode register and extended mode registers should be
loaded prior to applying any operational command because
it will power up in an unknown state.
COMMAND INHIBIT
AUTO REFRESH
cycles are complete, the SDRAM is then
cycles must be performed. After
or a
NOP
. The COMMAND
20
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Page 21
IS42S81600A, IS42S16800A, IS42S32400A
INITIALIZE AND LOAD MODE REGISTER
®
ISSI
CLK
CKE
COMMAND
DQML, DQMH
DQM/
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
tCKS tCKH
tCMH tCMS tCMH tCMS tCMH tCMS
NOP
T
Power-up: V
and CLK stable
T = 100µs Min.
PRECHARGE
ALL BANKS
SINGLE BANK
ALL BANKS
CC
Precharge
all banks
NOP NOP NOP ACTIVE
tCH
AUTO
REFRESH
AUTO REFRESH AUTO REFRESH Program MODE REGISTER
tCLtCK
AUTO
REFRESH
Load MODE
REGISTER
tAS tAH
CODE
tAS tAH
CODE
tMRDtRFCtRFCtRP
DON'T CARE
ROW
ROW
BANK
(2, 3, 4)
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IS42S81600A, IS42S16800A, IS42S32400A
AUTO-REFRESH CYCLE
T0 T1 T2 Tn+1 To+1
tCLtCK
CLK
CKE
COMMAND
tCKS tCKH
tCMS tCMH
PRECHARGE
NOP NOP NOP ACTIVE
tCH
Auto
Refresh
Auto
Refresh
®
ISSI
DQML, DQMH
DQM/
A0-A9, A11
A10
BA0, BA1
DQ
ALL BANKS
SINGLE BANK
(s)
BANK
tAS tAH
High-Z
ROW
ROW
BANK
tRP
DON'T CARE
22
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Page 23
IS42S81600A, IS42S16800A, IS42S32400A
SELF-REFRESH CYCLE
T0 T1 T2 Tn+1 To+1 To+2
t
CLK
CKE
COMMAND
t
CK
t
CKS tCKH
t
CMS tCMH
PRECHARGE
NOP NOP NOP
CH
t
t
CL
CKS
Auto
Refresh
≥ t
RAS
t
CKS
®
ISSI
Auto
Refresh
DQML, DQMH
DQM/
A0-A9, A11
A10
BA0, BA1
DQ
Precharge all
active banks
ALL BANKS
SINGLE BANK
tAS t
AH
BANK
High-Z
t
RP
Enter self
refresh
mode
CLK stable prior to exiting
self refresh mode
t
XSR
Exit
self refresh
mode
(Restart refresh time base)
DON'T CARE
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23
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IS42S81600A, IS42S16800A, IS42S32400A
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in MODE
REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
ISSI
(sequential or interleaved)
, M4- M6
®
BA1 BA0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Reserved
Address Bus
Mode Register (Mx)
(1)
Burst Type
M3 Type
0 Sequential
1 Interleaved
Latency Mode
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Burst Length
M2 M1 M0 M3=0 M3=1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
24
Operating Mode
M8 M7 M6-M0 Mode
0 0 Defined Standard Operation
— — — All Other States Reserved
Write Burst Mode
M9 Mode
0 Programmed Burst Length
1 Single Location Access
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1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0, 0"
PRELIMINARY INFORMATION Rev. 00C
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Page 25
IS42S81600A, IS42S16800A, IS42S32400A
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A7 (x32)
when the burst length is set to two; by A2-A7 (x32) when the
burst length is set to four; and by A3-A7 (x32) when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in BURST DEFINITION table.
®
ISSI
BURST DEFINITION
Burst Starting Column Order of Accesses Within a
Burst
Length Address Type = Sequential Type = Interleaved
A0
2 0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n = A0-A7 Cn, Cn + 1, Cn + 2 Not Supported
Page Cn + 3, Cn + 4...
(y) (location 0-y) …Cn - 1,
Cn…
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IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n +
m. The DQs will start driving as a result of the clock edge
one cycle earlier
access times are met, the data will be valid by clock edge
n +
m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
(n + m
- 1), and provided that the relevant
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed CAS Latency = 2 CAS Latency = 3
6 - 166
7 100 143
10 100 100
CAS LATENCY
CLK
COMMAND
DQ
CLK
COMMAND
DQ
T0 T1 T2 T3
READ NOP NOP
t
AC
D
OUT
t
CAS Latency - 2
T0 T1 T2 T3 T4
READ NOP NOP NOP
LZ
CAS Latency - 3
tOH
t
t
AC
D
OUT
LZ
tOH
DON'T CARE
26
UNDEFINED
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Page 27
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
CHIP OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a
bank within the SDRAM, a row in that bank must be
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank
After opening a row
READ or WRITE command may be issued to that row,
subject to the tRCD specification. Minimum tRCD should be
divided by the clock period and rounded up to the next whole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a tRCD specification of 20ns
with a 125 MHz clock (8ns period) results in 2.5 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The
same procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank
is defined by tRC.
(issuing an ACTIVE command)
“opened.”
).
, a
ACTIVATING SPECIFIC ROW WITHIN SPECIFIC BANK
CLK
HIGH
CKE
CS
RAS
CAS
WE
A0-A11
BA0, BA1
ROW ADDRESS
BANK ADDRESS
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by tRRD.
EXAMPLE: MEETING TRCD (MIN) WHEN 2
T0 T1 T2 T3 T4
CLK
COMMAND
ACTIVE NOP NOP
tRCD
<<
< [TRCD (MIN)/TCK]
<<
READ or
WRITE
≤≤
≤ 3
≤≤
DON'T CARE
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PRELIMINARY INFORMATION Rev. 00C
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27
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IS42S81600A, IS42S16800A, IS42S32400A
READ COMMANDREADS
READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram.
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled
or disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the
burst. For the generic READ commands used in the following
illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the CAS
latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. The
CAS Latency diagram shows general timing
for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows
either the last element of a completed burst or the last desired
data element of a longer burst which is being truncated.
The new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Consecutive READ Bursts for CAS latencies of
two and three; data element n + 3 is either the last of a burst
of four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the
ture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as shown
in Random READ Accesses, or each subsequent READ
may be performed to a different bank.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a
single-cycle delay should occur between the last read data
and the WRITE command.
2n
rule associated with a prefetch architec-
The DQM input is used to avoid I/O contention, as shown in
Figures RW1 and RW2. The DQM signal must be asserted
(HIGH) at least two clocks prior to the WRITE command
(DQM latency is two clocks for output buffers) to suppress
data-out from the READ. Once the WRITE command is
registered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal, provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQM was LOW during T4 in Figure RW2, then the WRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to
ensure that the written data is not masked. Figure RW1
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure RW2 shows the case where the additional NOP is
needed.
A fixed-length READ burst may be followed by, or truncated
with, a
that auto precharge was not activated)
may be truncated with a PRECHARGE command to the
CLK
CKE
CS
RAS
CAS
WE
A0-A7
A8, A9, A11
A10
BA0, BA1
PRECHARGE
HIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
BANK ADDRESS
command to the same bank
, and a full-page burst
®
ISSI
(provided
28
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PRELIMINARY INFORMATION Rev. 00C
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Page 29
IS42S81600A, IS42S16800A, IS42S32400A
same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency minus
one. This is shown in the READ to PRECHARGE diagram for
each possible CAS latency; data element
last of a burst of four or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note
that part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time
(as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the
command; the advantage of the PRECHARGE command is
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
n
+ 3 is either the
®
ISSI
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29
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IS42S81600A, IS42S16800A, IS42S32400A
RW1 - READ TO WRITE
T0 T1 T2 T3 T4
CLK
DQM
®
ISSI
COMMAND
ADDRESS
DQ
READ
NOP NOP NOP WRITE
BANK,
COL n
RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE
T0 T1 T2 T3 T4 T5
CLK
tHZ
DOUT n
BANK,
COL b
DON'T CARE
DIN b
tDS
30
DQM
COMMAND
ADDRESS
DQ
READ
NOP NOP NOP NOP WRITE
BANK,
COL n
tHZ
DOUT n
Integrated Silicon Solution, Inc. — www.issi.com —
BANK,
COL b
DIN b
tDS
DON'T CARE
PRELIMINARY INFORMATION Rev. 00C
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Page 31
IS42S81600A, IS42S16800A, IS42S32400A
CONSECUTIVE READ BURSTS
T0 T1 T2 T3 T4 T5 T6
CLK
®
ISSI
COMMAND
ADDRESS
CLK
COMMAND
ADDRESS
DQ
READ
NOP NOP NOP READ NOP NOP
x = 1 cycle
BANK,
COL n
DQ
CAS Latency - 2
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP READ NOP NOP NOP
BANK,
COL n
CAS Latency - 3
D
OUT
n
D
OUT
n+1 D
DOUT n
BANK,
COL b
OUT
n+2 D
x = 2 cycles
BANK,
COL b
DOUT n+1 DOUT n+2
OUT
n+3
DOUT n+3
D
DON'T CARE
OUT
b
DOUT b
DON'T CARE
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31
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IS42S81600A, IS42S16800A, IS42S32400A
RANDOM READ ACCESSES
T0 T1 T2 T3 T4 T5
CLK
®
ISSI
COMMAND
ADDRESS
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP NOP
DQ
BANK,
COL n
BANK,
COL b
BANK,
COL m
DOUT n
BANK,
COL x
DOUT b
DOUT m
DOUT x
CAS Latency - 2
DON'T CARE
T0 T1 T2 T3 T4 T5 T6
READ
READ
READ
READ
NOP NOP NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
D
OUT
n
D
OUT
b
D
OUT
m
D
OUT
CAS Latency - 3
DON'T CARE
x
32
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IS42S81600A, IS42S16800A, IS42S32400A
READ BURST TERMINATION
T0 T1 T2 T3 T4 T5 T6
CLK
®
ISSI
COMMAND
ADDRESS
CLK
COMMAND
ADDRESS
DQ
READ
NOP NOP NOP NOP NOP
BANK a,
COL n
DQ
CAS Latency - 2
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP NOP
BANK,
COL n
CAS Latency - 3
D
OUT
n
D
OUT
n+1
TERMINA TE
DOUT n
BURST
TERMINA TE
x = 1 cycle
D
OUT
n+2
BURST
x = 2 cycles
DOUT n+1 DOUT n+2
D
OUT
n+3
DON'T CARE
DOUT n+3
DON'T CARE
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IS42S81600A, IS42S16800A, IS42S32400A
ALTERNATING BANK READ ACCESSES
®
ISSI
CLK
CKE
COMMAND
DQML, DQMH
DQM/
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CL
t
CH
ACTIVE
NOP READ NOP
t
CMS tCMH
(2)
COLUMN m
ROW
COLUMN b
(2)
ROW ROW
BANK 0 BANK 3 BANK 3 BANK 0
t
LZ
D
OUT
t
AC
CAS Latency - BANK 0
t
OH
m D
t
AC
t
RCD
- BANK 3
t
OH
OUT
m+1 D
t
AC
t
OH
OUT
m+2 D
t
AC
tRP - BANK 0
CAS Latency - BANK 3
OUT
t
OH
m+
3
t
AC
t
CKS tCKH
t
CMS tCMH
ACTIVE
tAS t
ROW
tAS t
ROW
tAS t
BANK 0
t
CK
NOP READ NOP
AH
AH
AH
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
t
RCD
- BANK 0
t
RRD
t
RAS
- BANK 0
tRC - BANK 0
ACTIVE
ROW
t
OH
D
OUT
b
t
AC
t
RCD
- BANK 0
DON'T CARE
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
34
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IS42S81600A, IS42S16800A, IS42S32400A
READ - FULL-PAGE BURST
®
ISSI
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4
t
t
CK
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP READ NOP NOP NOP NOP NOP
tAS t
AH
ROW
tAS t
AH
CL
t
CH
t
CMS tCMH
(2)
COLUMN m
BURST TERM NOP NOP
ROW
tAS t
AH
BANK
t
RCD
BANK
t
AC
t
LZ
CAS Latency
t
AC
D
OUT
m D
t
OH
each row (x4) has
1,024 locations
t
AC
OUT
m+1 D
t
OH
Full page
completion
t
AC
OUT
m+2 D
t
OH
Full-page burst not self-terminating.
Use BURST TERMINATE command.
OUT
m-
t
OH
t
AC
1
t
AC
D
OUT
m D
t
OH
OUT
m+
t
OH
t
HZ
1
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
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IS42S81600A, IS42S16800A, IS42S32400A
READ - DQM OPERATION
®
ISSI
CLK
CKE
COMMAND
DQML, DQMH
DQM/
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CL
t
CH
t
CKS tCKH
t
CMS tCMH
t
CK
ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
CMS tCMH
t
tAS t
AH
ROW
tAS t
AH
ENABLE AUTO PRECHARGE
(2)
COLUMN m
ROW
tAS t
BANK
AH
DISABLE AUTO PRECHARGE
BANK
t
RCD
t
AC
t
LZ
CAS Latency
t
D
OUT
OH
m+2
t
AC
t
OH
D
OUT
m+
3
t
HZ
t
OH
D
OUT
m
t
HZ
t
AC
t
LZ
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
36
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IS42S81600A, IS42S16800A, IS42S32400A
READ to PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
®
ISSI
t
RP
COMMAND
ADDRESS
DQ
CLK
COMMAND
ADDRESS
DQ
READ
NOP NOP NOP NOP NOP ACTIVE
BANK a,
COL n
DOUT n
DOUT n+1 DOUT n+2
CAS Latency - 2
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP ACTIVE
BANK,
COL n
DOUT n
CAS Latency - 3
PRECHARGE
x = 1 cycle
BANK
(a or all)
PRECHARGE
BANK,
COL b
DOUT n+1 DOUT n+2
DOUT n+3
x = 2 cycles
BANK a,
ROW
DON'T CARE
t
RP
BANK a,
ROW
DOUT n+3
DON'T CARE
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IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
WRITES
WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.
WRITE COMMAND
CLK
HIGH
CKE
CS
RAS
CAS
WE
A0-A7
A8, A9, A11
A10
BA0, BA1
The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid
registered coincident
data elements will be registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored
(see WRITE Burst). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0
and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
provided coincident with the new command applies to the new
command.
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
BANK ADDRESS
with the
WRITE
data-in
element will be
command.
Subsequent
An example is shown in WRITE to WRITE diagram. Data
+ 1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined
architecture and therefore does not require the
associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within
a page can be performed to the same bank, as shown in
Random WRITE Cycles, or each subsequent WRITE may
be performed to a different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ com mand is registered, the
data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n +
1 is either the last of a burst of two or the last desired of a
longer burst.
Data for a fixed-length WRITE burst may be followed by, or
truncated with, a PRECHARGE command to the same bank
(provided that auto precharge was not activated), and a fullpage WRITE burst may be truncated with a PRECHARGE
command to the same bank. The PRECHARGE command
should be issued t
desired input data element is registered. The auto precharge
mode requires a tWR of at least one clock plus time,
regardless of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask input
data for the clock edge prior to, and the clock edge coincident
with, the PRECHARGE command. An example is shown in the
WRITE to PRECHARGE diagram. Data n+1 is either the last
of a burst of two or the last desired of a longer burst. Following
the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time
described above)
from the same fixed-length burst with auto precharge. The
disadvantage of the
that the command and address buses be available at the
appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
data written (provided that DQM is LOW at that time) will be
the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data n is the last desired data element
of a longer burst.
WR after the clock edge at which the last
provides the same operation that would result
PRECHARGE
command is that it requires
2n
rule
(as
n
38
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IS42S81600A, IS42S16800A, IS42S32400A
WRITE BURST
T0 T1 T2 T3
CLK
®
ISSI
WRITE TO WRITE
COMMAND
ADDRESS
DQ
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN n
CLK
NOP
DIN n+1
T0 T1 T2
WRITE
BANK,
COL n
NOP
NOP
DON'T CARE
WRITE
BANK,
COL b
NOP
DQ
DIN n
RANDOM WRITE CYCLES
T0 T1 T2 T3
CLK
COMMAND
ADDRESS
DQ
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WRITE
BANK,
COL n
DIN n
WRITE
BANK,
COL b
DIN b
DIN n+1
DON'T CARE
WRITE
BANK,
COL m
DIN m
1-800-379-4774
DIN b
WRITE
BANK,
COL x
DIN x
39
Page 40
IS42S81600A, IS42S16800A, IS42S32400A
WRITE TO READ
T0 T1 T2 T3 T4 T5
CLK
®
ISSI
COMMAND
ADDRESS
DQ
Latency = 2
WRITE
BANK,
COL n
DIN n
NOP
DIN n+1
WRITE TO PRECHARGE (TWR @ TCK
T0 T1 T2 T3 T4 T5 T6
CLK
DQM
READ
BANK,
COL b
≥ ≥
≥ 15NS)
≥ ≥
NOP
NOP NOP
DOUT b
DOUT b+1
DON'T CARE
40
COMMAND
ADDRESS
DQ
tRP
tWR
PRECHARGE
BANK
(a or all)
BANK a,
ROW
WRITE
NOP NOP NOP ACTIVE NOP
BANK a,
COL n
DIN n
DIN n+1
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Page 41
IS42S81600A, IS42S16800A, IS42S32400A
WRITE to PRECHARGE (tWR @ tCK < 15ns)
T0 T1 T2 T3 T4 T5 T6
CLK
DQM
®
ISSI
tRP
COMMAND
ADDRESS
DQ
WRITE
BANK a,
COL n
DIN n
DIN n+1
WRITE Burst Termination
NOP PRECHARGE NOP NOP ACTIVE
NOP
tWR
BANK
(a or all)
BANK a,
ROW
DON'T CARE
T0 T1 T2
CLK
COMMAND
WRITE
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
BANK,
COL n
DIN n
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(ADDRESS)
(DATA)
DON'T CARE
1-800-379-4774
41
Page 42
IS42S81600A, IS42S16800A, IS42S32400A
WRITE - FULL PAGE BURST
T0 T1 T2 T3 T4 T5 Tn+1 Tn+2
t
CLK
CKE
t
CKS tCKH
t
CMS tCMH
t
CK
CL
t
CH
®
ISSI
COMMAND
ACTIVE NOP WRITE NOP NOP NOP NOP
DQM/DQML
DQMH/DQM0-3
tAS t
AH
A0-A9, A11
A10
BA0, BA1
ROW
tAS t
ROW
tAS t
BANK
AH
AH
DQ
t
RCD
Notes:
1) Burst Length = Full Page
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
t
CMS tCMH
(2)
COLUMN m
BANK
tDS t
DH
tDS t
tDS tDHtDS t
DH
DIN m DIN m+1 DIN m+2 DIN m+
Full page completed
DH
tDS tDHtDS t
3
DIN m-
BURST TERM NOP
DH
1
DON'T CARE
42
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Page 43
IS42S81600A, IS42S16800A, IS42S32400A
WRITE - DQM OPERATIOON
T0 T1 T2 T3 T4 T5 T6 T7
tCLtCK
CLK
tCKS tCKH
CKE
tCMS tCMH
tCH
®
ISSI
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
DQ
tRCD
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
t
CMS tCMH
(2)
COLUMN m
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
tDS tDH tDS tDH tDS tDH
DIN m DIN m+2 DIN m+3
DON'T CARE
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43
Page 44
IS42S81600A, IS42S16800A, IS42S32400A
ALTERNATING BANK WRITE ACCESS
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
CL
t
CH
t
CKS tCKH
t
CMS tCMH
t
CK
ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
CMS tCMH
t
tAS t
AH
(2)
ROW
tAS t
AH
ROW
tAS t
AH
BANK 0
COLUMN m
ROW
COLUMN b
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
ROW ROW
BANK 0 BANK 1 BANK 1 BANK 0
tDS t
t
RCD
t
RRD
t
RAS
- BANK 0
- BANK 0
DH
tDS t
DH
tDS t
DIN m DIN m+1 DIN m+2 DIN m+
DH
t
RCD
tDS t
DH
3
tWR - BANK 0 tRP - BANK 0
- BANK 1
(2)
ROW
tDS tDHtDS tDHtDS tDHtDS t
DIN b DIN b+1 DIN b+2 DIN b+
tRC - BANK 0
DON'T CARE
DH
3
t
RCD
- BANK 0
tWR - BANK 1
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
44
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Page 45
IS42S81600A, IS42S16800A, IS42S32400A
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
T0 T1 T2 T3 T4 T5
CLK
CKE
INTERNAL
CLOCK
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
®
ISSI
COMMAND
ADDRESS
DQ
NOP
WRITE
BANK a,
COL n
DIN n
Clock Suspend During READ Burst
T0 T1 T2 T3 T4 T5 T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
NOP NOP NOP NOP NOP
NOP NOP
DIN n+1 DIN n+2
DON'T CARE
DQ
BANK a,
COL n
Qn
Qn+1 Qn+2 Qn+3
ADDRESS
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DON'T CARE
45
Page 46
IS42S81600A, IS42S16800A, IS42S32400A
CLOCK SUSPEND MODE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
CLK
CKE
t
CKS tCKH
t
CMS tCMH
t
CK
CL
t
CKS tCKH
t
CH
®
ISSI
COMMAND
READ NOP NOP NOP NOP NOP WRITE NOP
CMS tCMH
t
DQM/DQML
DQMH/DQM0-3
tAS t
AH
A0-A9, A11
(2)
COLUMN m
tAS t
AH
A10
tAS t
AH
BA0, BA1
BANK BANK
DQ
Notes:
1) CAS latency = 2, Burst Length = 2
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
(2)
COLUMN n
tDS t
D
OUT
DH
e
D
OUT
e+1
t
AC
D
OUT
t
LZ
t
AC
m D
t
OH
t
OUT
HZ
m+1
DON'T CARE
UNDEFINED
46
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Page 47
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
PRECHARGE
The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that
bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if powerdown occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
device may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See figure below.
PRECHARGE Command
CLK
CKE
RAS
CAS
A0-A9, A11
BA0, BA1
HIGH
CS
WE
ALL BANKS
A10
BANK SELECT
BANK ADDRESS
POWER-DOWN
CLK
t
CKS
CKE
COMMAND
All banks idle
Enter
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NOP NOP
Input buffers gated
power-down mode
less than 64ms
CKS
≥ t
off
Exit power-down mode
1-800-379-4774
ACTIVE
DON'T CARE
t
RCD
t
RAS
t
RC
47
Page 48
IS42S81600A, IS42S16800A, IS42S32400A
POWER-DOWN MODE CYCLE
T0 T1 T2 Tn+1 Tn+2
tCLtCK
CLK
tCH
®
ISSI
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
Precharge all
active banks
tCKS tCKH
tCMS tCMH
PRECHARGE
ALL BANKS
SINGLE BANK
tAS tAH
BANK
High-Z
NOP NOP NOP
Two clock cycles
All banks idle, enter
power-down mode
Input buffers gated
off while in
power-down mode
Exit power-down mode
tCKStCKS
ACTIVE
ROW
ROW
BANK
All banks idle
DON'T CARE
48
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Page 49
IS42S81600A, IS42S16800A, IS42S32400A
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit
In this mode, all
(M9)
in the mode register to a logic 1.
WRITE
commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
READ With Auto Precharge interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2. Interrupted by a WRITE (with or without auto precharge):
®
ISSI
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n when
registered. DQM should be used two clocks prior to the
WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
COMMAND
BANK n
NOP NOP NOP NOP NOP NOP
Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
READ - AP
BANK n
READ - AP
BANK m
Internal States
BANK m
ADDRESS
DQ
Page Active READ with Burst of 4 Precharge
BANK n,
COL a
CAS Latency - 3 (BANK n)
BANK n,
COL b
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
COMMAND
BANK n
Internal States
BANK m
READ - AP
NOP NOP NOP NOP NOP NOP
BANK n
READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active
Page Active WRITE with Burst of 4 Write-Back
tRP - BANK n tRP - BANK m
DOUT a
DOUT a+1
DOUT b
DOUT b+1
DON'T CARE
WRITE - AP
BANK m
t
RP - BANK n
t
WR - BANK m
ADDRESS
DQM
DQ
BANK n,
COL a
CAS Latency - 3 (BANK n)
D
OUT
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BANK m,
COL b
a
DIN b
1-800-379-4774
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
49
Page 50
IS42S81600A, IS42S16800A, IS42S32400A
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing
The PRECHARGE to bank n will begin after t
(CAS latency)
WR is met,
later.
where tWR begins when the READ to bank m is registered.
The last valid
WRITE
to bank n will be data-in registered one
clock prior to the READ to bank m.
WRITE With Auto Precharge interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
4. Interrupted by a WRITE (with or without auto precharge):
®
ISSI
A
WRITE
to bank m will interrupt a
registered. The PRECHARGE to bank n will begin after tWR
is met, where tWR begins when the WRITE to bank m is
registered. The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m.
WRITE
on bank n when
COMMAND
BANK n
Internal States
BANK m
ADDRESS
DQ
NOP NOP NOP NOP NOP NOP
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
WRITE - AP
BANK n
Page Active READ with Burst of 4 Precharge
BANK n,
COL a
DIN a
DIN a+1
READ - AP
BANK m
BANK m,
COL b
tWR - BANK n
CAS Latency - 3 (BANK m)
WRITE With Auto Precharge interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
COMMAND
NOP NOP NOP NOP NOP NOP
WRITE - AP
BANK n
WRITE - AP
BANK m
t
RP - BANK n
D
OUT
b
D
DON'T CARE
t
RP - BANK m
OUT
b+1
50
BANK n
Internal States
BANK m
ADDRESS
DQ
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tWR - BANK n
Page Active WRITE with Burst of 4 Write-Back
BANK n,
COL a
DIN a
DIN a+1 DIN a+2
BANK m,
COL b
DIN b
DIN b+1 DIN b+2 DIN b+3
t
RP - BANK n
t
WR - BANK m
DON'T CARE
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Page 51
IS42S81600A, IS42S16800A, IS42S32400A
SINGLE READ WITH AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
tAS t
ROW
tAS t
ROW
tAS t
BANK
t
CK
AH
AH
AH
t
RCD
t
RAS
t
RC
t
CL
t
CH
t
CMS tCMH
(2)
COLUMN m
ENABLE AUTO PRECHARGE
BANK
D
CAS Latency
t
AC
t
OUT
t
RP
OH
m
t
ROW
ROW
BANK
HZ
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
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51
Page 52
IS42S81600A, IS42S16800A, IS42S32400A
READ WITH AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CL
t
CH
t
CKS tCKH
t
CMS tCMH
t
CK
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
CMS tCMH
t
tAS t
AH
ROW
tAS t
ROW
tAS t
BANK
AH
AH
(2)
COLUMN m
ENABLE AUTO PRECHARGE
BANK
t
RCD
t
RAS
t
RC
t
AC
t
LZ
CAS Latency
D
OUT
t
OH
m
t
AC
D
OUT
t
m+1
t
OH
AC
t
AC
D
OUT
m+2 D
t
OH
t
RP
OUT
m+3
t
OH
ROW
ROW
BANK
t
HZ
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
52
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Page 53
IS42S81600A, IS42S16800A, IS42S32400A
SINGLE READ WITHOUT AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
t
CK
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP READ NOP NOP
tAS t
AH
ROW
tAS t
AH
ROW
tAS t
AH
BANK
t
RCD
t
RAS
t
RC
CL
t
CH
t
CMS tCMH
(2)
COLUMN m
DISABLE AUTO PRECHARGE
BANK
t
LZ
CAS Latency
PRECHARGE
NOP ACTIVE NOP
ROW
ALL BANKS
ROW
SINGLE BANK
BANK
t
D
OH
OUT
m
t
HZ
t
RP
t
AC
BANK
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
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53
Page 54
IS42S81600A, IS42S16800A, IS42S32400A
READ WITHOUT AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
t
CK
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP READ NOP NOP NOP
tAS t
AH
ROW
tAS t
AH
CL
t
CH
t
CMS tCMH
(2)
COLUMN m
PRECHARGE
NOP ACTIVE
ALL BANKS
ROW
tAS t
BANK
AH
DISABLE AUTO PRECHARGE
BANK
t
RCD
t
RAS
t
RC
CAS Latency
SINGLE BANK
BANK
t
AC
t
LZ
D
OUT
t
OH
m
t
AC
D
OUT
t
m+1
t
OH
AC
t
AC
D
OUT
m+2 D
t
OH
t
HZ
OUT
m+3
t
OH
t
RP
ROW
ROW
BANK
DON'T CARE
UNDEFINED
Notes:
1) CAS latency = 2, Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
54
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IS42S81600A, IS42S16800A, IS42S32400A
SINGLE WRITE WITH AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
t
CK
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP WRITE NOP
tAS t
AH
ROW
tAS t
AH
ROW
tAS t
AH
BANK
t
RCD
t
RAS
t
RC
CL
t
CH
(4)
CMS tCMH
t
(3)
COLUMN m
ENABLE AUTO PRECHARGE
NOP
(4)
SINGLE BANK
PRECHARGE
NOP
ROW
ALL BANKS
BANK BANK BANK
tDS t
DH
IN
m
D
(3)
t
WR
t
ACTIVE
NOP
ROW
RP
DON'T CARE
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
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55
Page 56
IS42S81600A, IS42S16800A, IS42S32400A
SINGLE WRITE - WITHOUT AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
t
CK
t
CKS tCKH
t
CMS tCMH
ACTIVE NOP WRITE NOP
tAS t
AH
ROW
tAS t
AH
ROW
tAS t
AH
BANK
t
RCD
t
RAS
t
RC
CL
t
CH
(4)
CMS tCMH
t
(3)
COLUMN m
ENABLE AUTO PRECHARGE
NOP
(4)
ALL BANKS
SINGLE BANK
PRECHARGE
NOP
ROW
BANK BANK BANK
tDS t
DH
IN
m
D
(3)
t
WR
t
ACTIVE
NOP
ROW
RP
DON'T CARE
Notes:
1) Burst Length = 1
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
56
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 57
IS42S81600A, IS42S16800A, IS42S32400A
WRITE - WITHOUT AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
CL
t
CH
t
CMS tCMH
COLUMN m
PRECHARGE
NOP
(3)
ALL BANKS
t
CKS tCKH
t
CMS tCMH
ACTIVE
tAS t
AH
ROW
tAS t
AH
t
CK
NOP WRITE NOP NOP NOP
ROW
tAS t
AH
BANK
DISABLE AUTO PRECHARGE
BANK
t
DS tDH
DIN m DIN m+1 DIN m+2 DIN m+
t
RCD
t
RAS
t
RC
tDS t
DH
tDS t
DH
tDS t
SINGLE BANK
DH
3
(2)
t
WR
BANK BANK
t
RP
ACTIVE
ROW
ROW
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
57
Page 58
IS42S81600A, IS42S16800A, IS42S32400A
WRITE - WITH AUTO PRECHARGE
®
ISSI
CLK
CKE
COMMAND
DQM/DQML
DQMH/DQM0-3
A0-A9, A11
A10
BA0, BA1
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
CL
t
CH
CMS tCMH
t
COLUMN m
(2)
t
CKS tCKH
t
CMS tCMH
ACTIVE
tAS t
ROW
tAS t
t
CK
NOP WRITE NOP NOP NOP NOP NOP NOP
AH
AH
ENABLE AUTO PRECHARGE
ROW
tAS t
AH
BANK
t
t
t
RCD
RAS
RC
BANK
DS tDH
t
tDS t
DH
tDS t
DH
tDS t
DIN m DIN m+1 DIN m+2 DIN m+
DH
3
t
WR
t
RP
ACTIVE
ROW
ROW
BANK
DON'T CARE
Notes:
1) Burst Length = 4
2) X16: A9 and A11 = "Don't Care"
X32: A8, A9, and A11 = "Don't Care"
58
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 59
IS42S81600A, IS42S16800A, IS42S32400A
ORDERING INFORMATION - VDD = 3.3V
®
ISSI
Commercial Range: 0
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S81600A-6T 54-Pin TSOPII
143 MHz 7 IS42S81600A-7T 54-Pin TSOPII
100 MHz 10 IS42S81600A-10T 54-Pin TSOPII
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S16800A-6T 54-Pin TSOPII
143 MHz 7 IS42S16800A-7T 54-Pin TSOPII
100 MHz 10 IS42S16800A-10T 54-Pin TSOPII
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S32400A-6T 86-Pin TSOPII
143 MHz 7 IS42S32400A-7T 86-Pin TSOPII
100 MHz 10 IS42S32400A-10T 86-Pin TSOPII
°°
°C to 70
°°
°°
°C
°°
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S81600A-7TI 54-Pin TSOPII
100 MHz 10 IS42S81600A-10TI 54-Pin TSOPII
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S16800A-7TI 54-Pin TSOPII
100 MHz 10 IS42S16800A-10TI 54-Pin TSOPII
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S32400A-7TI 86-Pin TSOPII
100 MHz 10 IS42S32400A-10TI 86-Pin TSOPII
°°
°C to 85
°°
°°
°C
°°
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
59
Page 60
IS42S81600A, IS42S16800A, IS42S32400A
ORDERING INFORMATION - VDD = 3.3V
®
ISSI
Commercial Range: 0
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S81600A-6TL 54-Pin TSOPII, Lead-free
143 MHz 7 IS42S81600A-7TL 54-Pin TSOPII, Lead-free
100 MHz 10 IS42S81600A-10TL 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S16800A-6TL 54-Pin TSOPII, Lead-free
143 MHz 7 IS42S16800A-7TL 54-Pin TSOPII, Lead-free
100 MHz 10 IS42S16800A-10TL 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S32400A-6TL 86-Pin TSOPII, Lead-free
143 MHz 7 IS42S32400A-7TL 86-Pin TSOPII, Lead-free
100 MHz 10 IS42S32400A-10TL 86-Pin TSOPII, Lead-free
°°
°C to 70
°°
°°
°C
°°
ORDERING INFORMATION - VDD = 3.3V
Industrial Range: -40
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S81600A-7TLI 54-Pin TSOPII, Lead-free
100 MHz 10 IS42S81600A-10TI 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S16800A-7TLI 54-Pin TSOPII, Lead-free
100 MHz 10 IS42S16800A-10TLI 54-Pin TSOPII, Lead-free
Frequency Speed (ns) Order Part No. Package
143 MHz 7 IS42S32400A-7TLI 86-Pin TSOPII, Lead-free
100 MHz 10 IS42S32400A-10TLI 86-Pin TSOPII, Lead-free
°°
°C to 85
°°
°°
°C
°°
60
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
Page 61
P ACKAGING INFORMA TION ISSI
D
SEATING PLANE
b
e
C
1
N/2
N/2+1N
E1
A1
A
E
L
α
ZD
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and
measured from the bottom of the
package
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
.
should be
®
Plastic TSOP (T - Type II)
Millimeters Inches
Symbol Min Ma x Min Max
Ref. Std.
No. Leads (N) 54
Symbol Min Max Min Max
Ref. Std.
No. Leads (N) 86
Plastic TSOP (T - Type II)
Millimeters Inches
A — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006
A2 — — — —
b 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.0083
D 22.02 22.42 0.867 0.8827
E1 10.03 10.29 0.395 0.405
E 11.56 11.96 0.455 0.471
e 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024
L1 — — — —
ZD 0.71 REF
α 0° 8° 0° 8°
A — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
b 0.17 0.27 0.007 0.011
C 0.12 0.21 0.005 0.008
D 22.02 22.42 0.867 0.8827
E1 10.16 BSC 0.400 BSC
E 11.56 11.96 0.455 0.471
e 0.50 BSC 0.020 BSC
L 0.40 0.60 0.016 0.024
L1 0.80 REF 0.031 REF
ZD 0.61 REF 0.024 BSC
α 0° 8° 0° 8°
Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. C
01/28/02
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