• Four CAS inputs for Byte Write and Byte Read
control
• Refresh modes: RAS-Only, CAS-Before-RAS (CBR),
and Hidden
• 512-cycle refresh in 8 ms
• Fast Page Mode with Extended Data Out
• 100-pin PQFP, TQFP package
DESCRIPTION
The ISSI IS41LV32256 is organized in a 262,122 x 32-bit
CMOS Dynamic Random Access Memory. Four CAS signals
facilitate execution of Byte Read and Byte Write operations.
A very fast EDO cycle time of 10 ns allows an operating
frequency of 100 MHz and makes the IS41LV32256 an ideal
frame buffer memory for graphics applications.
The IS41LV32256 is compatible with JEDEC standard
SGRAMs. This 8-Mbit EDO memory offers a significantly
lower latency and a faster memory cycle than the SGRAM.
ISSI's IS41LV32256 3.3V 256K x 32 device is pin/voltage
compatible with all standard SGRAM parts.
The IS41LV32256 is available in a 100-pin PQFP and TQFP
package.
KEY TIMING PARAMETERS
Parameter-28-30-35Unit
Max. RAS Access Time (tRAC)283035ns
Max. CAS Access Time (tCAC)9910ns
Max. Column Address Access Time (tAA)151618ns
Max. OE Access Time (tOE)9910ns
Min. Read/Write Cycle Time (tRC)485360ns
Min. EDO Cycle Time (tPC)121215ns
The initial application of the VCC supply requires a 200-µs
wait followed by a minimum of any eight initialization
cycles containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS.
It is recommended that RAS and CAS track with VCC or be
held at a valid VIH during Power-On to avoid current
surges.
®
ABSOLUTE MAXIMUM RATINGS
(1)
SymbolParametersRatingUnit
tAAmbient Temperature Under Bias–1.0 to +80°C
tSTGStorage Temperature–50 to +125°C
VTVoltage Relative to GND–1.0 to +5.5V
IOUTData Output Current50mA
PDPower Dissipation1.0W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(1)
(TA = 0°C to 70°C)
SymbolParameterMin.Typ.Max.Unit
VCCPower Supply3.03.33.6V
VIHInput High Voltage2.4—VCC + 0.5V
VILInput Low Voltage–0.5—0.4V
tCASCAS Pulse Width
tCPCAS Precharge Time
tCSHCAS Hold Time
tRCDRAS to CAS Delay Time
tASRRow-Address Setup Time0—0—0—ns
tRAHRow-Address Hold Time6—6—7—ns
(20)
(20)
0—0—0—ns
5—5—6—ns
tASCColumn-Address Setup Time
tCAHColumn-Address Hold Time
tARColumn-Address Hold Time21—22—25—ns
(referenced to RAS)
tRADRAS to Column-Address Delay Time
(11)
813815916ns
tRALColumn-Address to RAS Lead Time15—16—18—ns
tRPCRAS to CAS Precharge Time0—0—0—ns
tRSHRAS Hold Time
tCLZCAS to Output in Low-Z
tCRPCAS to RAS Precharge Time
tODOutput Disable Time
tOEOutput Enable Time
(15, 29)
(19, 28, 29)
(15, 16)
(21)
3—3—3—ns
5—5—5—ns
315315315ns
—9—9—10ns
tOEHCOE HIGH Hold Time from CAS HIGH10—10—10—ns
tOEPOE HIGH Pulse Width10—10—10—ns
tOESOE LOW to CAS HIGH Setup Time5—5—5—ns
tRCSRead Command Setup Time
(17, 20)
0—0—0—ns
tRRHRead Command Hold Time0—0—0—ns
(referenced to RAS)
(12)
tRCHRead Command Hold Time0—0—0—ns
(referenced to CAS)
tWCHWrite Command Hold Time
(12, 17, 21)
(17, 27)
5—5—5—ns
tWCRWrite Command Hold Time21—22—24—ns
(referenced to RAS)
tWPWrite Command Pulse Width
(17)
(17)
5—5—6—ns
tWPZWE Pulse Widths to Disable Outputs10—10—10—ns
(14, 17, 20)
(17)
(17, 21)
7—7—8—ns
5—5—8—ns
0—0—0—ns
tRWLWrite Command to RAS Lead Time
tCWLWrite Command to CAS Lead Time
tWCSWrite Command Setup Time
tDHRData-in Hold Time (referenced to RAS)21 —22—24—ns
tACHColumn-Address Setup Time to CAS15—15—15—ns
Precharge during WRITE Cycle
tOEHOE Hold Time from WE during5—5—6—ns
READ-MODIFY-WRITE cycle
tDSData-In Setup Time
tDHData-In Hold Time
(15, 22)
(15, 22)
(18)
0—0—0—ns
5—5—6—ns
tRWCREAD-MODIFY-WRITE Cycle Time73—73—80—ns
tRWDRAS to WE Delay Time during40—40—45—ns
READ-MODIFY-WRITE Cycle
tCWDCAS to WE Delay Time
(14, 20)
tAWDColumn-Address to WE Delay Time
(14)
(14)
18—18—20—ns
24—25—30—ns
tPCEDO Page Mode READ or WRITE12—12—15—ns
Cycle Time
(24)
tRASPRAS Pulse Width in EDO Page Mode28100K30100K35100Kns
tCPAAccess Time from CAS Precharge
(15)
—17—18—21ns
tPRWCEDO Page Mode READ-WRITE34—35—40—ns
Cycle Time
(24)
tCHOData Output Hold after CAS LOW3—3—3—ns
tOFFOutput Buffer Turn-Off Delay from3737315ns
returning HIGH
tCSRCAS Setup Time (CBR REFRESH)
tCHRCAS Hold Time (CBR REFRESH)
(23)
(30, 20)
(30, 21)
5—5—8—ns
7—7—8—ns
tORDOE Setup Time prior to RAS during0—0—0—ns
HIDDEN REFRESH Cycle
tREFRefresh Period (512 Cycles)—8—8—8ms
tTTransition Time (Rise or Fall)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
IL (or between VIL and VIH) and assume to be 1 ns for all inputs.
V
3. In addition to meeting the transition rate specification, all input signals must transit between V
in a monotonic manner.
4. If CAS and RAS = V
5. If CAS = V
IL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
the amount that t
8. Assumes that tRCD• tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for t
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the t
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either t
13. t
RCH or tRRH must be satisfied for a READ cycle.
OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS• tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD• tRWD
(MIN), tAWD• tAWD (MIN) and tCWD• tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
IH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
to V
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after t
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IH, data output is High-Z.
RCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
RCD exceeds the value shown.
RAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
(2, 3)
OEH is met.
150150150ns
REF refresh requirement is exceeded.
IH and VIL (or between VIL and VIH)
CP.
OD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
8
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
Page 9
IS41LV32256ISSI
READ CYCLE (Outputs Controlled by RAS)
t
RC
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
RRH
t
RP
®
ADDRESS
WE
I/O
OE
RowColumnRow
t
t
RCS
t
AA
t
RAC
t
CAC
t
CLC
OpenOpen
t
OE
t
OES
Valid Data
RCH
t
OFF
t
(1)
OD
Don't Care
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
9
Page 10
IS41LV32256ISSI
READ CYCLE (Outputs Controlled by CAS)
t
RC
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
RRH
t
RP
®
ADDRESS
WE
I/O
OE
RowColumnRow
t
t
RCS
t
AA
t
RAC
t
CAC
t
CLC
OpenOpen
t
OE
t
OES
Valid Data
RCH
t
OFF
t
(1)
OD
Don't Care
10
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
Page 11
IS41LV32256ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
t
RAH
RAD
t
RCD
t
ASC
t
AR
RAS
t
CSH
t
CAS
t
RAL
t
CAH
t
ACH
t
RSH
t
CLCH
t
RP
®
ADDRESS
WE
I/O
RowColumnRow
t
CWL
t
RWL
t
WCR
t
t
WP
t
DH
WCH
t
WCS
t
DHR
t
DS
Valid Data
Don't Care
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
11
Page 12
IS41LV32256ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RWC
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
ACH
t
RP
®
ADDRESS
WE
I/O
OE
RowColumnRow
t
RWD
t
t
RCS
t
AA
t
RAC
t
CAC
t
CLZ
OpenOpen
t
OE
CWD
t
AWD
Valid D
t
OD
t
OUT
DS
Valid D
t
CWL
t
RWL
t
WP
t
DH
IN
t
OEH
Undefined
Don't Care
12
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
Page 13
IS41LV32256ISSI
EDO-PAGE-MODE READ CYCLE
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
RAD
t
RCD
t
ASC
RASP
t
CSH
t
CAS,
t
CLCH
t
AR
t
CAH
t
ASC
t
CP
t
PC
(1)
t
CAS,
t
CLCH
t
CAH
t
ASC
t
RSH
t
t
CP
CAS,
t
CLCH
t
RAL
t
CAH
t
RP
t
CP
®
ADDRESS
RowRow
t
RAH
ColumnColumn
t
RCS
Column
t
RCH
t
RRH
WE
t
I/O
AA
t
RAC
t
CAC
t
CLZ
OpenOpen
t
OE
t
OES
t
t
Valid Data
CAC
COH
t
AA
t
CPA
t
OEHC
t
CAC
t
CLZ
Valid Data
t
OD
t
AA
t
CPA
t
OES
Valid Data
t
OE
t
OFF
t
OD
OE
t
OEP
Undefined
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the t
PC specifications.
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
13
Page 14
IS41LV32256ISSI
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RAS
CAS0-CAS3
t
CRP
t
ASR
t
RAD
t
RCD
t
ASC
RASP
t
CSH
t
CAS,
t
CLCH
t
AR
t
ACH
t
CAH
t
ASC
t
CP
t
PC
t
CAS,
t
CLCH
t
ACH
t
CAH
t
ASC
t
CP
t
t
ACH
t
t
RAL
t
RSH
CAS,
CLCH
t
CAH
t
RP
t
CP
®
ADDRESS
WE
I/O
OE
RowRow
t
RAH
ColumnColumn
t
CWL
t
WCS
t
WCH
t
WP
t
WCR
t
DHR
t
DS
t
DH
Valid Data
t
DS
Column
t
CWL
t
WCS
t
WCH
t
WP
t
DH
Valid Data
t
DS
t
WCH
t
DH
Valid Data
t
CWL
t
WCS
t
WP
t
RWL
Don't Care
14
Integrated Silicon Solution, Inc.
Rev. A
09/29/00
Page 15
IS41LV32256ISSI
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
®
RAS
CAS0-CAS3
ADDRESS
WE
I/O
OE
tRASP
tAWD
tCAS, tCLCHtCAS, tCLCH
tCAHtCAH
tCWD
tDS
(1)
tCWL
tWP
tDH
tRSH
tCAS, tCLCH
tRAL
tAA
tAWD
tCAH
tCWD
tDS
tRWL
tCWL
tWP
tDH
DINDOUT
tOD
tASC
tCPA
tCAC
tCLZ
DINDOUT
tOD tOD
tCP
tCAC
tCLZ
tPC / tPRWC
Column
tAA
tCPA
tCRP
tASR
tRAH
tRAD
RowRow
OpenOpen
tCSH
tRCD
tAR
ColumnColumn
tRWD
tRCStCWL
tAA
tRAC
tCAC
tCLZ
tOE tOE tOE
tAWD
tCWD
tDS
tWP
tDH
tASCtASC
DINDOUT
tRP
tCPtCP
tOEH
Undefined
Don't Care
Note:
PC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both