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IS41LV16257-35KI
Datasheet (ISSI)
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Datasheet IS41LV16257-35KI, IS41LV16257-35K, IS41LV16257-60TI, IS41LV16257-60T, IS41LV16257-60K Datasheet (ISSI)

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Page 1
IS41C16257
®
IS41LV16257
256K x 16 (4-MBIT) DYNAMIC RAM WITH F AST PAGE MODE
FEATURES
• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
•
Refresh Mode: and Hidden
• JEDEC standard pinout
• Single power supply:
-- 5V ± 10% (IS41C16257)
-- 3.3V ± 10% (IS41LV16257)
• Byte Write and Byte Read operation via two
• Industrial temperature available
-Only,
CAS
-before-
(CBR),
CAS
DESCRIPTION
The ISSI IS41C16257 and the IS41LV16257 are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes these devices ideal for use in 16- and 32-bit wide data bus systems.
These features make the IS41C16257 and the IS41LV16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications.
The IS41C16257 and the IS41LV16257 are packaged in a 40-pin, 400-mil SOJ and TSOP (Type II).
ISSI
MAY 1999
KEY TIMING PARAMETERS
Parameter -35 -60 Unit
Max.
RAS
Access Time (tRAC)3560ns
Max.
CAS
Access Time (tCAC)1015ns Max. Column Address Access Time (tAA)1830ns Min. Fast Page Mode Cycle Time (tPC)1225ns Min. Read/Write Cycle Time (tRC) 60 110 ns
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
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1
Page 2
IS41C16257 IS41LV16257
FUNCTIONAL BLOCK DIAGRAM
OE WE
®
ISSI
LCAS UCAS
RAS
A0-A8
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
REFRESH COUNTER
ADDRESS BUFFERS
WE
CAS WE
RAS
CONTROL
LOGICS
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
262,144 x 16
ROW DECODER
OE
CONTROL
LOGIC
OE
I/O0-I/O15
DATA I/O BUFFERS
PIN CONFIGURATIONS 40-Pin TSOP (Type II)
VCC
I/O0 I/O1 I/O2 I/O3
VCC
I/O4 I/O5 I/O6 I/O7
NC NC
WE
RAS
NC
A0 A1 A2 A3
VCC
1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31
30 29 28 27 26 25 24 23 22 21
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
40-Pin SOJ
1
VCC
2
I/O0
3
I/O1
4
I/O2
5
I/O3
6
VCC
7
I/O4
8
I/O5
9
I/O6
10
I/O7
11
NC
12
NC
13
WE
14
RAS
15
NC
16
A0
17
A1
18
A2
19
A3
20
VCC
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A8 Address Inputs I/O0-I/O15 Data Inputs/Outputs
WE OE RAS
UCAS Upper Column Address
LCAS
Vcc Power GND Ground NC No Connection
Write Enable Output Enable Row Address Strobe
Strobe Lower Column Address
Strobe
2
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Page 3
IS41C16257 IS41LV16257
TRUTH TABLE
®
ISSI
Function
Standby H H H X X X High-Z Read: Word L L L H L ROW/COL DOUT Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Write: Word (Early Write) L L L L X ROW/COL DIN Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Read-Write Hidden Refresh
RAS
CBR Refresh
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
2. These READ cycles may also be BYTE READ cycles (either
3. At least one of the two CAS signals must be active (
(1,2)
2)
-Only Refresh L H H X X ROW/NA High-Z
(3)
Read L→H→L L L H L ROW/COL DOUT
Write L→H→LLLLXROW/COLDOUT
RASRAS
RAS
RASRAS
LLLH→LL→H ROW/COL DOUT, DIN
H→L L L X X X High-Z
LCASLCAS
LCAS
LCASLCAS
LCAS
UCASUCAS
UCAS
UCASUCAS
LCAS
or
UCAS
LCAS
WEWE
WE
WEWE
or
).
or
UCAS
OEOE
OE
OEOE
UCAS
active).
Address tR/tC I/O
Upper Byte, High-Z
Upper Byte, DOUT
Upper Byte, High-Z
Upper Byte, DIN
active).
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3
Page 4
IS41C16257 IS41LV16257
FUNCTIONAL DESCRIPTION
®
ISSI
The IS41C16257 and the IS41LV16257 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered nine bits (A0-A8) at a time. The row address is latched by the Row Address Strobe ( latched by the Column Address Strobe ( to latch the first nine bits and nine bits.
The IS41C16257 and the IS41LV16257 has two controls, internally generate a manner to the single DRAMs. The key difference is that each corresponding I/O tristate logic (in conjunction with OE and
WE
controls I/O8 - I/O15. The IS41C16257 and the IS41LV16257
determined by the first LOW and the last transitioning back HIGH. The two controls give the IS41C16257 both BYTE READ and BYTE WRITE cycle capabilities.
and
LCAS
RAS
).
and
LCAS
RAS
). The column address is
CAS
).
RAS
CAS
is used to latch the latter
UCAS
. The
LCAS
and
UCAS
CAS
signal functioning in an identical
CAS
input on the other 256K x 16
CAS
controls its
controls I/O0 - I/O7 and
CAS
function is
CAS (LCAS
or
UCAS
) transitioning
is used
CAS
inputs
UCAS
CAS
Memory Cycle
A memory cycle is initiated by bringing terminated by returning both ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
RAS
RAS
and
LOW and it is
CAS
HIGH. To
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of whichever occurs last. The input data must be valid at or before the falling edge of
CAS
or WE, whichever occurs last.
CAS
and WE,
Refresh Cycle
To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through A8) with read-modify-write or dressed row.
2. Using a
RAS
holding internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS
-before­or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
RAS
at least once every 8 ms. Any read, write,
RAS
-only cycle refreshes the ad-
CAS
-before-
refresh is activated by the falling edge of
CAS
LOW. In
RAS
is a refresh-only mode and no data access
RAS
refresh cycle.
CAS
-before-
CAS
RAS
refresh cycle, an
-before-
RAS
, while
Power-On
After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
During power-on, it is recommended that or be held at a valid VIH to avoid current surges.
RAS
RAS
track with VCC
signal).
Read Cycle
A read cycle is initiated by the falling edge of whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent
4
CAS
or OE,
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Page 5
IS41C16257 IS41LV16257
®
ISSI
ABSOLUTE MAXIMUM RATINGS
Symbol Parameters Rating Unit
VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
VCC Supply Voltage 5V –1.0 to +7.0 V
IOUT Output Current 50 mA PD Power Dissipation 1 W TA Operation Temperature Com. 0 to 70 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(1)
3.3V –0.5 t0 +4.6
3.3V –0.5 t0 +4.6
Ind. –40 to +85
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND)
Symbol Parameter Voltage Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V VCC Supply Voltage 3.3V 3.0 3.3 3.6 V
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V VIH Input High Voltage 3.3V 2.0 — VCC + 0.3 V VIL Input Low Voltage 5V –1.0 — 0.8 V VIL Input Low Voltage 3.3 –0.3 — 0.8 V
TA Ambient Temperature Com. 0 — 70 °C
Ind. –40 — 85
CAPACITANCE
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A8 5 pF CIN2 Input Capacitance: CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
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(1,2)
RAS, UCAS, LCAS, WE, OE
A = 25°C, f = 1 MHz, VCC = 5.0V + 10% or Vcc=3.3V ± 10%.
7pF
5
Page 6
IS41C16257 IS41LV16257
®
ISSI
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V < VIN < Vcc –10 10 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA
0V < VOUT < Vcc VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V VOL Output Low Voltage Level IOL = 2.1 mA — 0.4 V
ICC1 Stand-by Current: TTL
RAS, LCAS, UCAS
≥ VIH Com. 5V — 2 mA
Ind. 5V 3
ICC1 Stand-by Current: TTL
RAS, LCAS, UCAS
≥ VIH Com. 3.3V — 1 mA
Ind. 3.3V 2 ICC2 Stand-by Current: CMOS ICC2 Stand-by Current: CMOS ICC3 Operating Current:
Random Read/Write
(2,3,4)
RAS, LCAS, UCAS RAS, LCAS, UCAS RAS, LCAS, UCAS
≥ VCC – 0.2V 5V — 2 mA ≥ VCC – 0.2V 3.3V — 1 mA , -35 — 230 mA
Address Cycling, tRC = tRC (min.) -60 — 170
Average Power Supply Current
ICC4 Operating Current:
Fast Page Mode
(2,3,4)
RAS
= VIL,
LCAS, UCAS
, -35 — 220 mA
Cycling tPC = tPC (min.) -60 — 160
Average Power Supply Current
ICC5 Refresh Current:
-Only
(2,3)
RAS
RAS
Cycling,
LCAS, UCAS
≥ VIH -35 — 230 mA
tRC = tRC (min.) -60 — 170
Average Power Supply Current
ICC6 Refresh Current:
(2,3,5)
CBR
RAS, LCAS, UCAS
Cycling -35 — 230 mA
tRC = tRC (min.) -60 — 170
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
operation is assured.The eight
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
RAS
cycles wake-up should be repeated any time the t
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
REF
refresh requirement is exceeded.
6
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Page 7
IS41C16257 IS41LV16257
®
ISSI
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless
otherwise noted.)
-35 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 60 — 110 — ns
(21)
RAS CAS
(26)
(6, 7) (6, 8, 15)
(9, 25)
(10, 20)
—35 —60 ns —10 —15 ns
(6)
—18 —30 ns
6 10K 10 10K ns
5— 10— ns 35 — 60 — ns 11 28 20 45 ns
tRAC Access Time from tCAC Access Time from tAA Access Time from Column-Address tRAS tRP tCAS tCP tCSH tRCD
RAS
Pulse Width 35 10K 60 10K ns
RAS
Precharge Time 20 — 40 — ns
CAS
Pulse Width
CAS
Precharge Time
CAS
Hold Time
RAS
to
CAS
Delay Time tASR Row-Address Setup Time 0 — — 0 — ns tRAH Row-Address Hold Time 6 — 10 — ns
(20)
(20)
0— 0— ns 6— 10— ns
tASC Column-Address Setup Time tCAH Column-Address Hold Time tAR Column-Address Hold Time 30 — 40 — ns
(referenced to
RAS
)
tRAD tRAL Column-Address to tRPC tRSH tCLZ tCRP tOD Output Disable Time tOE Output Enable Time tOEHC tOEP tOES
RAS
to Column-Address Delay Time
RAS
Lead Time 18 — 30 — ns
RAS
to
CAS
Precharge Time 0 — 0 — ns
RAS
Hold Time
CAS
to Output in Low-Z
CAS
to
OE
HIGH Hold Time from
OE
HIGH Pulse Width 10 — 10 — ns
OE
LOW to
(27)
RAS
Precharge Time
(19, 28, 29)
(15, 16)
CAS
HIGH Setup Time 5 — 5 — ns
(15, 29)
CAS
tRCS Read Command Setup Time
(11)
12 20 15 30 ns
8— 15— ns 3— 3— ns
(21)
5— 5— ns 315 315 ns
—10 —15 ns
HIGH 10 — 10 — ns
(17, 20)
0— 0— ns
tRRH Read Command Hold Time 0 — 0 — ns
(referenced to
RAS
)
(12)
tRCH Read Command Hold Time 0 — 0 — ns
(referenced to
tWCH Write Command Hold Time
CAS
(12, 17, 21)
)
(17, 27)
5— 10— ns
tWCR Write Command Hold Time 30 — 50 — ns
(referenced to tWP Write Command Pulse Width tWPZ
WE
Pulse Widths to Disable Outputs 10 — 10 — ns tRWL Write Command to tCWL Write Command to tWCS Write Command Setup Time tDHR Data-in Hold Time (referenced to
RAS
(17)
)
RAS
Lead Time
CAS
Lead Time
(17)
(14, 17, 20)
RAS
5— 10— ns
(17)
(17, 21)
8— 15— ns 8— 15— ns 0— 0— ns
)30—40—ns
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(Continued)
7
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IS41C16257 IS41LV16257
®
ISSI
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless
otherwise noted.)
-35 -60
Symbol Parameter Min. Max. Min. Max. Units
tACH Column-Address Setup Time to
CAS
15 — 15 — ns
Precharge during WRITE Cycle
tOEH
tDS Data-In Setup Time tDH Data-In Hold Time
OE
Hold Time from WE during 8 — 15 — ns
READ-MODIFY-WRITE cycle
(15, 22)
(15, 22)
(18)
0— 0— ns
6— 10— ns tRWC READ-MODIFY-WRITE Cycle Time 80 — 140 — ns tRWD
tCWD tAWD Column-Address to WE Delay Time
RAS
to WE Delay Time during 45 — 80 — ns
READ-MODIFY-WRITE Cycle
CAS
to WE Delay Time
(14, 20)
(14)
(14)
25 — 36 — ns 30 — 49 — ns
tPC Fast Page Mode READ or WRITE 12 — 25 — ns
Cycle Time
tRASP
RAS
tCPA Access Time from tPRWC READ-WRITE Cycle Time
(24)
Pulse Width 35 100K 60 100K ns
(24)
(15)
—21 —34 ns 40 — 56 — ns
CAS
Precharge
tOFF Output Buffer Turn-Off Delay from 3 15 3 15 ns
CAS
tWHZ Output Disable Delay from tCLCH Last
returning HIGH tCSR tCHR tORD
CAS
CAS
OE
Setup Time prior to
(13,15,19, 29)
or
RAS
WE
CAS
going LOW to First
(23)
Setup Time (CBR REFRESH) Hold Time (CBR REFRESH)
CAS
(30, 20)
(30, 21)
RAS
during 0 — 0 — ns
315 315 ns
10 — 10 — ns
8— 10— ns 8— 10— ns
HIDDEN REFRESH Cycle tREF Refresh Period (512 Cycles) — 8 — 8 ms tT Transition Time (Rise or Fall)
(2, 3)
150 150 ns
8
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Page 9
IS41C16257 IS41LV16257
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V IH and
IL (or between VIL and VIH) and assume to be 1 ns for all inputs.
V
3. In addition to meeting the transition rate specification, all input signals must transit between V in a monotonic manner.
4. If
5. If
CAS CAS
and
RAS
IL, data output may contain data from the last valid READ cycle.
= V
IH, data output is High-Z.
= V
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t the amount that t
RCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
RCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If
CAS
is LOW at the falling edge of
data output buffer,
CAS
and
RAS
RAS
, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
must be pulsed for t
CP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the t
RAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either t
13. t
RCH or tRRH must be satisfied for a READ cycle.
OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
IH) is indeterminate.
to V
15. Output parameter (I/O) is referenced to corresponding
16. During a READ cycle, if OE is LOW then taken HIGH before
OE
held HIGH and WE taken LOW after
CAS
input, I/O0-I/O7 by
CAS
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if and OE is taken back to LOW after t
OEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χ
21. The last χ
22. These parameters are referenced to
CAS
edge to transition LOW.
CAS
edge to transition HIGH.
CAS
leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χ
24. Last rising χ
25. Last rising χ
26. Each χ
27. Last χ
28. I/Os controlled, regardless
CAS
edge to first rising χ
CAS
edge to next cycle’s last rising χ
CAS
CAS
CAS
edge to first falling χ
must meet minimum pulse width.
to go LOW.
UCAS
and
CAS
CAS
LCAS
edge. edge.
.
CAS
edge.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
RAS
refresh cycle (
RAS
-Only or CBR) before proper device
REF refresh requirement is exceeded.
IH and VIL (or between VIL and VIH)
CAS
CAS
goes LOW result in a LATE WRITE (OE-controlled) cycle.
LCAS
and I/O8-I/O15 by
goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
OD and tOEH met (
OE
HIGH during WRITE cycle) in order to ensure
and
UCAS
RAS
CAS
ISSI
or OE go back
.
remains LOW
®
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9
Page 10
IS41C16257 IS41LV16257
FAST-PAGE-MODE READ CYCLE
RAS
t
CRP
UCAS/LCAS
t
RAD
t
t
ASR
RAH
t
RCD
t
ASC
®
ISSI
t
RC
t
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
RRH
t
RP
ADDRESS
Row Column Row
WE
I/O
OE
Note:
OFF is referenced from rising edge of
1. t
t
t
RCS
t
AA
t
RAC
t
CAC
t
CLC
Open Open
t
OE
t
OES
Valid Data
RCH
t
OFF
t
(1)
OD
Don't Care
CAS
.
10
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Page 11
IS41C16257 IS41LV16257
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
®
ISSI
RAS
UCAS/LCAS
ADDRESS
WE
OE
I/O0-I/O15
tCRP
tASR
tRAH
Row
tRAD
tRCS
tRCD
tAR
tRAC
Column
tAA
tCAC
tCLZ
tRASP
tCSH
tCAS tCAS tCAS
tCP tCP
tCPWD
tCAH
tASC
tAR
tCWL
tRWD
tAWD tCWD tCWD tCWD
tOEA
tOEZ tOEZ
tOED tOED
tCLZ
tDS
OUT ININ IN
tASC
Column Column
tWP
tAA
tCAC
tDH
tCAH
tCWL
tAWD tAWD
tWP
tAA
tCAC
tOEA
tDH tDH
tDS
OUT
tASC
tRP
tRSHtPRWC
tCRP
tCPWD
tRAL
tCAH
tCWL tRWL
tWP
tOEA
tOEZ
tOED
tDStCLZ
OUT
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Don't Care
11
Page 12
IS41C16257 IS41LV16257
®
ISSI
FAST-PAGE-MODE EARLY WRITE CYCLE (
RAS
t
UCAS/LCAS
ADDRESS
CRP
t
ASR
t
Row Column Row
t
RAD
RAH
t
RCD
t
ASC
t
OE
= DON'T CARE)
t
RAS
t
CSH
t
AR
t
WCR
WCS
t
t t
WP
t
RC
t
CAS
t
RAL
t
CAH
t
ACH
CWL RWL
t
WCH
t
RSH
t
CLCH
t
RP
WE
I/O
t
DHR
t
DS
Valid Data
t
DH
Don't Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
Page 13
IS41C16257 IS41LV16257
FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
RAS
tCSH
tRSH
tCAS
tCLCH
tACH
UCAS/LCAS
tCRP
tRCD
tAR
tRAD tRAL
tRAHtASR
tASC
tCAH
ISSI
®
tRP
ADDRESS
WE
I/O
OE
Row Column Row
tRWD tCWL
tRCS
tAA
tRAC
tCAC
tCLZ tDS tDH
Open Open
tOE
tCWD
tAWD tWP
Valid DOUT Valid DIN
Don't Care
tRWL
tOEHtOD
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B 05/24/99
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Page 14
IS41C16257 IS41LV16257
FAST PAGE MODE EARLY WRITE CYCLE
®
ISSI
RAS
UCAS/LCAS
ADDRESS
WE
OE
I/O0-I/O15
tCRP
tASR
tRAH
Row
tRAD
tWCS
tRCD
tDS
tAR
tWCR
tDHR
tCSH
tCAS tCAS tCAS
tCAH
tASC
Column
tCWL
tWCH
tWP tWP
tDH
Valid DIN
tCP
tAR
tWCS
tDS
tRASP
tPC
tCP
tASC
Column Column
Valid DIN Valid DIN
tCAH
tCWL
tWCS
tWCH
tWP
tDS
tDH tDH
tASC
tRP
tRHCP
tRSH
tCRP
tRAL
tCAH
tCWL
tWCH
Don't Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
Page 15
IS41C16257 IS41LV16257
AC WAVEFORMS
®
ISSI
READ CYCLE (With
RAS
tCRP
UCAS/LCAS
ADDRESS
WE
I/O
OE
WE
-Controlled Disable)
tRCD tCP
tRAD
tRAHtASR
Row Column
tASC
Open Open
tAR
tRAC
tCSH
tCAS
tCAH tASC
tRCH tRCStRCS
tAA
tCAC
tCLZ
tOE tOD
tWHZ
Valid Data
Column
tCLZ
RASRAS
RAS
-ONLY REFRESH CYCLE (
RASRAS
RAS
t
CRP
UCAS/LCAS
t
ADDRESS
I/O
ASR
Don't Care
OE, WE
Row Row
= DON'T CARE)
t
RAS
t
RAH
Open
t
RC
t
RP
t
RPC
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B 05/24/99
15
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IS41C16257 IS41LV16257
CBRCBR
CBR
REFRESH CYCLE (Addresses;
CBRCBR
RAS
t
RPC
t
CP
UCAS/LCAS
®
ISSI
WE, OE
t
RP
t
CHR
= DON'T CARE)
t
RAS
t
CSR
t
RPC
t
t
RP
t
CSR
RAS
t
CHR
I/O
HIDDEN REFRESH CYCLE
RAS
t
CRP
UCAS/LCAS
t
ASR
ADDRESS
I/O
Row Column
(1)
Open
(
WE
= HIGH; OE = LOW)
t
t
RAD
t
RAH
t
RCD
RAS
t
ASC
t
AR
t
RAL
t
AA
t
RAC
t
CAC
t
CLZ
t
CAH
t
RSH
t
RP
Open Open
t
OE
t
ORD
t
RAS
t
CHR
t
Valid Data
OFF
(2)
t
OD
OE
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
OFF is referenced from rising edge of
2. t
16
RAS
or
CAS
, whichever occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Don't Care
DR004-1B
05/24/99
Page 17
IS41C16257 IS41LV16257
®
ISSI
ORDERING INFORMATION IS41C16257 Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
35 IS41C16257-35K 400-mil SOJ
IS41C16257-35T 400-mil TSOP (Type II)
60 IS41C16257-60K 400-mil SOJ
IS41C16257-60T 400-mil TSOP (Type II)
Industrial Range: –40°C to 85°C
Speed (ns) Order Part No. Package
35 IS41C16257-35KI 400-mil SOJ
IS41C16257-35TI 400-mil TSOP (Type II)
60 IS41C16257-60KI 400-mil SOJ
IS41C16257-60TI 400-mil TSOP (Type II)
ORDERING INFORMATION IS41LV16257 Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
35 IS41LV16257-35K 400-mil SOJ
IS41LV16257-35T 400-mil TSOP (Type II)
60 IS41LV16257-60K 400-mil SOJ
IS41LV16257-60T 400-mil TSOP (Type II)
Industrial Range: –40°C to 85°C
Speed (ns) Order Part No. Package
35 IS41LV16257-35KI 400-mil SOJ
IS41LV16257-35TI 400-mil TSOP (Type II)
60 IS41LV16257-60KI 400-mil SOJ
IS41LV16257-60TI 400-mil TSOP (Type II)
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B 05/24/99
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774 Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
17
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