Datasheet IS41LV8200-50JI, IS41LV8200-50J, IS41C8200-50JI, IS41C8200-50J, IS41C8200-60JI Datasheet (ISSI)
...Page 1
IS41C8200
IS41LV8200 ISSI
2M x 8 (16-MBIT) DYNAMIC RAM
®
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• Single power supply:
5V±10% or 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial temperature range -40°C to 85°C
PRODUCT SERIES OVERVIEW
Part No. Refresh Voltage
IS41C8200 2K 5V ± 10%
IS41LV8200 2K 3.3V ± 10%
JUNE 2001
DESCRIPTION
The
ISSI
IS41C8200 and IS41LV8200 are 2,097,152 x 8-bit
highperformance CMOS Dynamic Random Access Memory.
These devices offer an accelarated cycle access called
EDO Page Mode. EDO Page Mode allows 2,048 random
accesses within a single row with access cycle time as
short as 20 ns per 4-bit word.
These features make the IS41C8200 and IS41LV8200
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C8200 and IS41LV8200 are packaged in 28-pin
300-mil SOJ with JEDEC standard pinouts.
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
RAS Access Time (tRAC)5060ns
CAS Access Time (tCAC)1315ns
PIN CONFIGURATION
28 Pin SOJ
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
A10
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
25 30 ns
20 25 ns
Read/Write Cycle Time (tRC) 84 104 ns
PIN DESCRIPTIONS
A0-A10 Address Inputs
I/O0-7 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe
Vcc Power
GND Ground
NC No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
1
Page 2
IS41C8200
IS41LV8200 ISSI
FUNCTIONAL BLOCK DIAGRAM
OE
WE
®
CAS
RAS
A0-A10
CAS
CONTROL
LOGIC
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
WE
CAS WE
RAS
CONTROL
LOGIC
COLUMN DECODER
SENSE AMPLIFIERS
ROW DECODER
OE
CONTROL
LOGIC
OE
DATA I/O BUS
I/O0-I/O7
DATA I/O BUFFERS
MEMORY ARRAY
2,097,152 x 8
TRUTH TABLE
Function RAS CAS WE OE Address tR/tC I/O
Standby H H X X X High-Z
Read L L H L ROW/COL DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Read-Write L L H→LL→H ROW/COL DOUT, DIN
EDO Page-Mode Read 1st Cycle: L H→L H L ROW/COL DOUT
2nd Cycle: L H→L H L NA/COL DOUT
EDO Page-Mode Write 1st Cycle: L H→ L L X ROW/COL DIN
2nd Cycle: L H→L L X NA/COL DIN
EDO Page-Mode 1st Cycle: L H→LH→LL→H ROW/COL DOUT, DIN
Read-Write 2nd Cycle: L H→LH→LL→H NA/COL DOUT, DIN
Hidden Refresh Read L→H→L L H L ROW/COL DOUT
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh H→L L X X X High-Z
Note:
1. EARLY WRITE only.
2
Write
(1)
L→H→L L L X ROW/COL DOUT
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 3
IS41C8200
IS41LV8200 ISSI
®
Functional Description
The IS41C8200 and IS41LV8200 are CMOS DRAMs
optimized for
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 address bits. These are entered
11 bits (A0-A10) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
ten bits.
high-speed bandwidth, low power applications.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write,
the addressed row.
2. Using a
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
read-modify-write
CAS-before-RAS
or
RAS-only
refresh cycle.
cycle refreshes
CAS-before-RAS
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing a RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
3
Page 4
IS41C8200
IS41LV8200 ISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
CC Supply Voltage 5V –1.0 to +7.0 V
V
3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PD Power Dissipation 1 W
A Commercial Operation Temperature 0 to +70 °C
T
Industrial Operation Temperature -40 to +85
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TA Commercial Ambient Temperature 0 — 70 °C
Industrial Ambient Temperature -40 — 85 °C
CAPACITANCE
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A10(A11) 5 pF
CIN2 Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
(1,2)
A = 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 5
IS41C8200
IS41LV8200 ISSI
®
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition VCC Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –55µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –55µA
0V ≤ VOUT ≤ Vcc
OH
V
Output High Voltage Level
IOH = –5.0 mA, Vcc = 5V 2.4 — V
IOH = –2.0 mA, Vcc = 3.3V
V
OL
Output Low Voltage Level
IOL = 4.2 mA, Vcc = 5V — 0.4 V
IOL = 2 mA, Vcc = 3.3V
ICC1 Standby Current: TTL RAS, CAS ≥ VIH
Commercial
5V 2 mA
3.3V — 0.5
Industrial
5V — 3
3.3V — 2
ICC2 Standby Current: CMOS RAS, CAS ≥ VCC – 0.2V 5V — 1mA
3.3V — 0.5
ICC3 Operating Current: RAS, CAS, -50 — 120 mA
Random Read/Write
(2,3,4)
Address Cycling, tRC = tRC (min.)
-60 — 110
Average Power Supply Current
ICC4 Operating Current: RAS= VIL, CAS ≥ VIH -50 — 90 mA
EDO Page Mode
(2,3,4)
tRC = tRC (min.) -60 — 80
Average Power Supply Current
ICC5 Refresh Current: RAS Cycling, CAS ≥ VIH -50 — 120 mA
RAS-Only
(2,3)
tRC = tRC (min.) -60 — 110
Average Power Supply Current
ICC6 Refresh Current: RAS, CAS Cycling -50 — 120 mA
(2,3,5)
CBR
tRC = tRC (min.) -60 — 110
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO Page cycle.
5. Enables on-chip refresh and address counters.
REF refresh requirement is exceeded.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
5
Page 6
IS41C8200
IS41LV8200 ISSI
®
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 84 — 104 — ns
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column-Address
(6, 7)
(6, 8, 15)
— 50 — 60 ns
— 13 — 15 ns
(6)
— 25 — 30 ns
tRAS RAS Pulse Width 50 10K 60 10K ns
tRP RAS Precharge Time 30 — 40 — ns
(21)
(23)
8 10K 10 10K ns
(9)
9 — 9 — ns
38 — 40 — ns
(10, 20)
12 37 14 45 ns
tCAS CAS Pulse Width
tCP CAS Precharge Time
tCSH CAS Hold Time
tRCD RAS to CAS Delay Time
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 8 — 10 — ns
(20)
(20)
0 — 0 — ns
8 — 10 — ns
tASC Column-Address Setup Time
tCAH Column-Address Hold Time
tAR Column-Address Hold Time 30 — 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time
(11)
10 25 12 30 ns
tRAL Column-Address to RAS Lead Time 25 — 30 — ns
tRPC RAS to CAS Precharge Time 5 — 5 — ns
tRSH RAS Hold Time 8 — 10 — ns
tRHCP RAS Hold Time from CAS Precharge 30 — 35 — ns
(19, 24)
(15, 16)
(15, 24)
(21)
0 — 0 — ns
5 — 5 — ns
315 315 ns
— 12 — 15 ns
tCLZ CAS to Output in Low-Z
tCRP CAS to RAS Precharge Time
tOD Output Disable Time
tOE Output Enable Time
tOED Output Enable Data Delay (Write) 12 — 15 — ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — ns
tOEP OE HIGH Pulse Width 10 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns
tRCS Read Command Setup Time
(17, 20)
0 — 0 — ns
tRRH Read Command Hold Time 0 — 0 — ns
(referenced to RAS)
(12)
tRCH Read Command Hold Time 0 — 0 — ns
(referenced to CAS)
tWCH Write Command Hold Time
(12, 17, 21)
(17)
8 — 10 — ns
tWCR Write Command Hold Time 40 — 50 — ns
(referenced to RAS)
tWP Write Command Pulse Width
(17)
(17)
8 — 10 — ns
tWPZ WE Pulse Widths to Disable Outputs 7 — 7 — ns
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 7
IS41C8200
IS41LV8200 ISSI
®
AC CHARACTERISTICS (Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
(14, 17, 20)
(17)
(17, 21)
13 — 15 — ns
8 — 10 — ns
0 — 0 — ns
tRWL Write Command to RAS Lead Time
tCWL Write Command to CAS Lead Time
tWCS Write Command Setup Time
tDHR Data-in Hold Time (referenced to RAS)39— 39 — ns
t
ACH Column-Address Setup Time to CAS 15 — 15 — ns
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during 8 — 10 — ns
READ-MODIFY-WRITE cycle
tDS Data-In Setup Time
tDH Data-In Hold Time
(15, 22)
(15, 22)
(18)
0 — 0 — ns
8 — 10 — ns
tRWC READ-MODIFY-WRITE Cycle Time 108 — 133 — ns
tRWD RAS to WE Delay Time during 64 — 77 — ns
(14, 20)
(14)
(14)
26 — 32 — ns
39 — 47 — ns
READ-MODIFY-WRITE Cycle
tCWD CAS to WE Delay Time
tAWD Column-Address to WE Delay Time
tPC EDO Page Mode READ or WRITE 20 — 25 — ns
Cycle Time
tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns
tCPA Access Time from CAS Precharge
tPRWC READ-WRITE Cycle Time
(24)
(15)
— 30 — 35 ns
56 — 68 — ns
tCOH Data Output Hold after CAS LOW 5 — 5 — ns
tOFF Output Buffer Turn-Off Delay from 0 12 0 15 ns
CAS or RAS
(13,15,19, 24)
tWHZ Output Disable Delay from WE 310 310 ns
tCSR CAS Setup Time (CBR REFRESH)
tCHR CAS Hold Time (CBR REFRESH)
(20, 25)
( 21, 25)
5 — 5 — ns
8 — 10 — ns
tORD OE Setup Time prior to RAS during 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period 2,048 Cycles — 32 — 32 ms
tT Transition Time (Rise or Fall)
(2, 3)
150 150 ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
7
Page 8
IS41C8200
IS41LV8200 ISSI
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
IH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
2. V
IL (or between VIL and VIH) and assume to be 1 ns for all inputs.
V
3. In addition to meeting the transition rate specification, all input signals must transit between V
monotonic manner.
4. If CAS and RAS = V
5. If CAS = V
IL, data output may contain data from the last valid READ cycle.
IH, data output is High-Z.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
amount that t
8. Assumes that t
RCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the
RCD exceeds the value shown.
RCD • tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for t
10. Operation with the t
greater than the specified t
11. Operation within the t
greater than the specified t
12. Either t
13. t
RCH or tRRH must be satisfied for a READ cycle.
OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
RCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
RCD (MAX) limit, access time is controlled exclusively by tCAC.
RAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
RAD (MAX) limit, access time is controlled exclusively by tAA.
CP.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • t RWD (MIN),
AWD • t AWD (MIN) and tCWD • t CWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected
t
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after t
OEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or
READ-MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
REF refresh requirement is exceeded.
IH and VIL (or between VIL and VIH) in a
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 9
IS41C8200
IS41LV8200 ISSI
READ CYCLE
tRC
RAS
CAS
tCRP
tRAS
tCSH
tRCD
tAR
tRAD tRAL
tRAHtASR
tASC
tCAS
tRSH
tCLCH
tCAH
tRP
tRRH
®
ADDRESS
Row Column
WE
tRAC
I/O
Open Open
OE
Note:
OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
1. t
tAA
tCAC
tCLC
Valid Data
tOE tOD
tOES
Row
tRCHtRCS
(1)
tOFF
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
9
Page 10
IS41C8200
IS41LV8200 ISSI
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
RWC
t
RAS
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
RAS
t
CSH
t
RSH
t
CAS
t
CLCH
t
AR
t
RAL
t
CAH
t
ACH
t
RP
®
ADDRESS
WE
I/O
OE
Row Column
t
RWD
t
RCS
t
AA
t
RAC
t
CAC
t
CLZ
Open Open
t
OE
t
CWD
t
AWD
Valid D
t
OD
t
OUT
DS
Valid D
IN
t
CWL
t
RWL
t
WP
t
DH
t
OEH
Don’t Care
Row
10
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Rev. B
06/22/01
Page 11
IS41C8200
IS41LV8200 ISSI
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RC
t
RAS
CAS
t
CRP
t
ASR
t
RAH
t
RAD
t
RCD
t
ASC
t
AR
RAS
t
CSH
t
CAS
t
RAL
t
CAH
t
ACH
t
RSH
t
CLCH
t
RP
®
ADDRESS
WE
I/O
Row Column
t
WCR
t
WCS
t
DHR
t
DS
Valid Data
t
CWL
t
RWL
t
WP
t
WCH
t
DH
Row
Don’t Care
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Rev. B
06/22/01
11
Page 12
IS41C8200
n
IS41LV8200 ISSI
EDO-PAGE-MODE READ CYCLE
t
RASP
RAS
t
RP
®
CAS
ADDRESS
WE
I/O
OE
t
CRP
t
ASR
t
CSH
t
t
AA
CAS,
t
CLCH
t
CAH
t
RCD
t
AR
t
RAD
t
ASC
Row Row
t
RAH
Column Column
t
RCS
t
RAC
t
CAC
t
CLZ
Open Ope
t
OE
t
OES
t
CP
t
ASC
t
CAC
t
COH
Valid Data
(1)
t
PC
Column
t
AA
t
CPA
t
CAS,
t
CLCH
t
t
OEHC
CAH
t
CP
t
ASC
t
CAC
t
CLZ
Valid Data
t
OD
t
OEP
t
AA
t
CPA
t
CAS,
t
CLCH
t
RAL
t
t
CAH
t
OES
RSH
t
RCH
Valid Data
t
OE
t
t
OFF
t
OD
t
CP
RRH
12
Don’t Care
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Rev. B
06/22/01
Page 13
IS41C8200
IS41LV8200 ISSI
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
CAS
ADDRESS
WE
I/O
OE
RASP
/ t
t
AWD
PRWC
t
t
t
CWD
D
(1)
CAS, tCLCH
CAH
t
CWL
t
WP
t
DH
t
DS
OUT
t
RSH
t
t
CP
t
ASC
t
CPA
t
CAC
t
CLZ
D
IN
t
OD
t
OE
CAS, tCLCH
t
RAL
t
CAH
t
RWL
t
CWL
t
WP
t
AWD
t
CWD
t
AA
t
DH
t
DS
D
OUT
IN
t
OD
D
t
t
CP
t
CAC
t
CLZ
t
CPA
t
OE
t
PC
Column
AA
t
CSH
t
CRP
t
ASR
t
RAH
t
RAD
t
t
RCD
ASC
t
AR
Row Row
t
RWD
t
RCS
t
RAC
t
CAC
t
CLZ
Open Open
t
OE
t
CAS, tCLCH
t
CAH
t
ASC
Column Column
t
CWL
t
WP
t
AWD
t
CWD
t
AA
t
DH
t
DS
D
OUT
t
IN
OD
D
t
OEH
t
RP
t
CP
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Don’t Care
13
Page 14
IS41C8200
IS41LV8200 ISSI
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RAS
CAS
t
CRP
t
ASR
t
RAD
t
RCD
t
ASC
t
AR
t
CSH
t
ACH
t
CAS,
t
CLCH
t
CAH
t
ASC
t
CP
RASP
t
PC
t
CAS,
t
CLCH
t
ACH
t
CAH
t
ASC
t
CP
t
t
t
ACH
t
RAL
t
RSH
CAS,
CLCH
t
CAH
t
RP
t
CP
®
ADDRESS
WE
I/O
OE
Row Row
t
RAH
t
Column Column
t
CWL
t
WCS
t
WCH
t
WP
t
WCR
t
DHR
DS
t
DH
t
Valid Data
DS
Column
t
CWL
t
WCS
t
WCH
t
WP
t
DH
Valid Data
t
DS
t
WCH
t
DH
Valid Data
t
CWL
t
WCS
t
WP
t
RWL
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 15
IS41C8200
IS41LV8200 ISSI
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
t
RAS
CAS
ADDRESS
WE
I/O
OE
RASP
t
CSH
t
t
t
CAH
t
CAS
PC
t
CP
t
ASC
t
Valid Data (A)
Column (B)
t
t
CPA
t
CAC
COH
AA
t
CRP
t
ASR
t
RAH
Row Row
t
RAD
t
RCD
t
AR
t
ASC
Column (A) Column (N)
t
RCS
t
AA
t
RAC
t
CAC
Open Open
t
OE
PC
t
CAS
t
CAH
t
RCH
t
WHZ
Valid Data (B)
t
ASC
t
t
t
DS
CP
WCS
t
RSH
t
CAS
t
ACH
t
RAL
t
CAH
t
WCH
t
DH
D
IN
t
RP
t
CP
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Don’t Care
15
Page 16
IS41C8200
IS41LV8200 ISSI
AC WAVEFORMS
®
READ CYCLE
RAS
CAS
ADDRESS
WE
I/O
(With WE-Controlled Disable)
tCRP
tRAD
tRAHtASR
Row Column
Open Open
tCSH
tRCD tCP
tAR
tASC
tAA
tRAC
tCAC
tCLZ
tCAS
tCAH tASC
tRCH tRCStRCS
tWHZ
Valid Data
tOE tOD
Column
tCLZ
OE
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
RAS
RAS
t
CRP
CAS
t
RAH
ADDRESS
I/O
t
ASR
Row
Open
t
RC
t
RPC
t
Don’t Care
RP
Row
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
Page 17
IS41C8200
IS41LV8200 ISSI
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
t
RAS
CAS
t
RPC
t
CP
t
RP
t
CHR
t
CSR
RAS
t
RPC
t
RP
t
CSR
t
RAS
t
CHR
®
I/O
HIDDEN REFRESH CYCLE
RAS
t
CRP
CAS
t
ASR
(1)
(WE = HIGH; OE = LOW)
t
RAS
t
RCD
t
AR
t
RAD
t
RAH
t
ASC
t
RAL
Open
t
CAH
t
RSH
t
RP
t
RAS
t
CHR
Don’t Care
ADDRESS
I/O
Row Column
Open Open
OE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
t
CLZ
t
RAC
t
OE
t
AA
t
CAC
t
ORD
t
Valid Data
OFF
(2)
t
OD
Don’t Care
17
Page 18
IS41C8200
IS41LV8200 ISSI
®
ORDERING INFORMATION
Commercial Range: 0
Voltage: 5V
Speed (ns) Order Part No. Package
50 IS41C8200-50J 300-mil SOJ
60 IS41C8200-60J 300-mil SOJ
Voltage: 3.3V
Speed (ns) Order Part No. Package
50 IS41LV8200-50J 300-mil SOJ
60 IS41LV8200-60J 300-mil SOJ
°°
°C to 70
°°
°°
°C
°°
ORDERING INFORMATION
Industrial Range: -40
Voltage: 5V
Speed (ns) Order Part No. Package
50 IS41C8200-50JI 300-mil SOJ
60 IS41C8200-60JI 300-mil SOJ
Voltage: 3.3V
Speed (ns) Order Part No. Package
50 IS41LV8200-50JI 300-mil SOJ
60 IS41LV8200-60JI 300-mil SOJ
°°
°C to 85°C
°°
18
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/22/01
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