Datasheet IRLU 8113 Datasheet (International Rectifier)

www.DataSheet4U.com

PD - 95779A

Absolute Maximum Ratings

Conti n uous Drai n Cur r e nt, V

@ 10V

Pulsed Drain Current

Thermal Resistance

Junction-to-Ambient (PCB Mount)

IRLR8113PbF IRLU8113PbF

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification for Telecom and Industrial Use

l Lead-Free

Benefits

l Very Low R l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage

(on) at 4.5V V

DS

GS

and Current

Parameter Units

V

DS

V

GS

@ TC = 25°C

I

D

@ TC = 100°C

I

D

I

DM

PD @TC = 25°C

@TC = 100°C

P

D

T

J

T

STG

Drain-to-Source Voltage V Gate-to-Source Voltage Conti n uous Drai n Cur r e nt, V

c

Maximum Power Dissipation W Maximum Power Dissipation

Linear D er ating Factor W/°C Operating Junction and °C

Stor ag e Temperat ur e Ra ng e Soldering Temperature, for 10 seconds

Mount ing torque, 6-32 or M 3 s crew

@ 10V

GS GS

HEXFET® Power MOSFET

V

DSS

R

DS(on)

30V

D-Pak

IRLR8113

Max.

30

± 20

f

94 67

f

380

89 44

0.59

-55 to + 175

300 (1. 6m m fr o m case)

x

in (1.1 Nxm)

10 lbf

6.0m

max

:

Qg

22nC

I-Pak

IRLU8113

A

R

JC

θ

R

JA

θ

R

JA

θ

Notes  through  are on page 11

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Parameter Typ. Max. Units

Junction-to-Case ––– 1.69

g

Junction-to-Ambient ––– 110

––– 50 °C/W

12/7/04

IRLR/U8113PbF

S

D

G

BV

V

/∆T

R

m

V

/∆T

I

Q

QswSwitch Charge (Q

+ Qgd)

Q

t

C

Avalanche Characteristics

EASSingle Pulse Avalanc h e E n er g y

IARAvalanche Current

EARRepeti ti ve Avalanche Energy

Diode Characterist ics

I

94

I

V

t

Q

t

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

DSS

∆Β

DSS

DS(on)

GS(th)

∆

GS(th)

DSS

GSS

gfs Forwa r d Transconductan c e 74 ––– ––– S

g

gs1 gs2 gd godr

oss d(on) r d(off) f

iss

oss

rss

Drain-to-Sou r c e Br e akdown Voltage 30 ––– ––– V Breakdown Voltage Temp. Coefficient ––– 21 ––– mV/°C

J

Stat ic D r ai n- to-Sou rce On-Res i s tance ––– 4.8 6.0

––– 5.8 7.4 Gate Thr es hold Voltage 1.35 ––– 2.25 V Gate Thr es hold Voltage Coef ficien t ––– -5.6 ––– mV /°C

J

Drain-to-Sou r c e Le akage Cur rent ––– ––– 1.0 µA

––– ––– 150 Gate-to-Sour c e Forward Lea k age ––– ––– 100 nA Gate-to-Sou rce Reverse Leaka ge ––– ––– -100

Total Gate Charge ––– 22 32 Pre-Vth Gate-to-Source Charge ––– 6.1 ––– Post-Vth Gate-to-Source Charge ––– 1.7 ––– nC Gate-to-Drain Char ge ––– 6.8 ––– Gate Cha r ge Ov e r drive ––– 7.4 ––– See Fig. 16

gs2

––– 8.5 ––– Output Charge ––– 14 ––– nC Turn- O n Delay Time ––– 9.2 ––– Rise Time ––– 3.8 –– – Turn-Off Delay Time ––– 15 ––– ns Fall Time ––– 10 ––– Input Capacitance ––– 2920 ––– Outpu t C ap ac itance ––– 610 ––– pF Reverse Transf er C ap ac itance ––– 260 –––

Conditions

VGS = 0V, ID = 250µA Reference to 25°C, I

Ω

V

= 10V, ID = 15A

GS

= 4.5V, ID = 12A

V

GS

VDS = VGS, ID = 250µA

V

= 24V, VGS = 0V

DS

V

= 24V, VGS = 0V, TJ = 175°C

DS

VGS = 20V V

= -20V

GS

V

= 15V, ID = 12A

DS

V

= 15V

DS

= 4.5V

V

GS

= 12A

I

D

= 16V, VGS = 0V

V

DS

V

= 15V, VGS = 4.5V

DD

ID = 12A Clampe d I n ductiv e Load

V

= 0V

GS

= 15V

V

DS

ƒ = 1.0MHz

= 1mA

D

e

S

SM

SD

rr

on

2 www.irf.com

Parameter Units

d

c

c

Para me ter Min. Typ . Max. Units

Contin uous Source Current ––– ––– (Body Diode) A

Pulsed Source Current ––– ––– 380 (Body Diode)

Diode Forward Voltage ––– ––– 1.0 V Reverse Recovery Time ––– 33 49 ns Reverse Recovery Charge ––– 30 45 nC

c

Typ.

––– ––– –––

Max.

145

13

8.9

mJ

A

mJ

Conditions

f

MOSFET symbol showing the

integral reverse p-n junct ion diode.

TJ = 25°C, IS = 12A, VGS = 0V T

= 25°C, IF = 12A, VDD = 15V

J

di/dt = 100A/µs

e

Forward Turn-On Time In trinsic turn-on time is negligible (turn-on is dominated by LS+LD)

e

IRLR/U8113PbF

1000

TOP 10V

) A

(

t

100

n

e

r

u C e

c

r

10

u

o S

-

o

t

-

n

i

a

r

1

D

,

D

I

2.5V

BOTTOM 2.5V

20µs PULSE WIDTH Tj = 25°C

0.1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

1000

)

Α

(

t

n

e

r

100

r

u C e

c

r

u

o S

-

o

t

-

n

10

i

a

r D

,

D

I

TJ = 25°C

V

DS

TJ = 175°C

= 15V

20µs PULSE WIDTH

1

2 3 4 5 6 7 8

VGS, Gate-to-Source Voltage (V)

VGS

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

) A

(

t

n

e

r

u C e

c

r

u

o S

-

o

t

-

n

i

a

r D

, I

D

1000

100

TOP 10V

BOTTOM 2.5V

2.5V

10

20µs PULSE WIDTH

VGS

4.5V

3.7V

3.5V

3.3V

3.0V

2.7V

Tj = 175°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

e

c

n

a

t

s

i

s

e R n O e

c

r

u

o S

-

o

t

-

n

i

a

r D

,

)

n

o

( S D

R

ID = 30A V

= 10V

GS

1.5

)

d

e

z

i

1.0

l

a m

r

o N

(

0.5

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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IRLR/U8113PbF

100000

) F

10000

p

(

e

c

n

a

t

i

c

a

p

a C

,

1000

C

100

V

= 0V, f = 1 MHZ

GS

C

= C

iss rss oss

= C

gs

gd

ds

C C

C

iss

C

oss

C

rss

1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

1000.00

) A

(

t

100.00

n

e

r

u C n

i

a

r D e

s

r

e

v

e R

,

D S

I

10.00

TJ = 175°C

TJ = 25°C

1.00

0.10

0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V)

+ Cgd, C

+ C

gd

SHORTED

ds

V

GS

= 0V

) V

( e

g

a

t

l

o V

e

c

r

u

o S

-

o

t

-

e

t

a G

,

S G

V

6.0 ID= 12A

5.0

4.0

3.0

2.0

1.0

0.0

0 5 10 15 20 25 30

VDS= 24V VDS= 15V

Q

Total G ate Charge (nC)

G

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

1000

) A

(

t

n

e

r

100

u C e

c

r

u

o S

-

o

t

-

n

10

i

a

r D ,

Tc = 25°C

D

I

Tj = 175°C Single Pulse

1

1 10 100

OPERATION IN THIS AREA LIMITED BY RDS(on)

VDS, Drain-to-Source Voltage (V)

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRLR/U8113PbF

100

90

Limited By Package

80

)

70

A

(

t

n

60

e

r

u C

50

n

i

a

r

40

D

,

30

D

I

20 10

0

25 50 75 100 125 150 175

TC , Case Temper ature (°C)

Fig 9. Maximum Drain Current vs.

Case Temperature

10

2.5

) V

( e

g

2.0

a

t

l

o V

d

l

o

h

s

1.5

e

r

h

t e

t

a G

)

h

1.0

t

( S G

V

0.5

-75 -50 -25 0 25 50 75 100 125 150 175 200

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage vs. Temperature

)

C

1

J

h

t

Z (

e

s

n

0.1

o

p

s

e R

l

a m

r

e

0.01

h T

0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJC C

1 2

P

DM

t

1

t

2

t1 , Rectangular Pulse Duration ( s ec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U8113PbF

S

Current Regulator

I

A

V 9

1 V

15V

V

DS

R

G

20V

V

GS

L

D.U.T

I

AS

Ω

0.01

t

p

DRIVER

+

V

DD

-

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

AS

Fig 12b. Unclamped Inductive Waveforms

700

)

J m

(

600

y

g

r

e

n

500

E e

h

c

n

400

a

l

a

v A

300

e

s

l

u P

e

200

l

g

n

i S

,

100

S A

E

0

25 50 75 100 125 150 175

TOP 8.3A

BOTTOM13A

Starting TJ , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

L

V

DS

D

I

D

9.4A

V

DD

D.U.T

V

Same Type as D.U.T.

12V

.2µF

V

GS

50KΩ

3mA

.3µF

D.U.T.

Fig 14a. Switching Time Test Circuit

+

V

D

-

DS

0%

GS

Pulse Width < 1µs

Duty Factor < 0.1%

0%

I

G

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

I

D

GS

t

d(on)tr

t

d(off)tf

Fig 14b. Switching Time Waveforms

6 www.irf.com

IRLR/U8113PbF

R V

+

-

Id





Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

e-Applied oltage

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P.W.

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRLR/U8113PbF

f

P P

f

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

⎛ ⎜

+ I ×

⎝

+ Qg× Vg× f

()

Q

⎛

+

⎝

This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

8 www.irf.com

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

⎞ ⎟

⎠

⎞ ⎠

and Q

gs1

+ P

+ I ×

+ P

drive

⎛

Q

gs2

⎜

i

⎝

g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin×

Synchronous FET

The power loss equation for Q2 is approximated

by;

= P

loss

conduction

= I

loss

+ Qg× Vg× f

+

rms

()

⎛ ⎜

⎝

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

⎞ ⎟

portance of gate charge must not be overlooked since

⎠

it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly , the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and of f there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

Q

oss

×Vin× f

2

gs1

Characteristic

oss

drive

must be minimized to reduce the

+ P

⎞ ⎠

*

output

+ Q

(

× Vin×

rr

ds(on)

oss

is an im-

and re-

D-Pak (TO-252AA) Package Outline

9

Dimensions are shown in millimeters (inches)

IRLR/U8113PbF

D-Pak (TO-252AA) Part Marking Information

EXAMPLE:

Note: "P" in assembly line position

www.irf.com 9

THIS IS AN IRFR120 WIT H ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A"

indicates "L ead-F ree"

OR

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT COD E

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT COD E

IRFU120

12 34

PART NUMBER

IRFU120

916A

12

34

PART NUMBER

DAT E CODE P = DESIGNATES LEAD-FREE

YEAR 9 = 1999 W EEK 1 6 A = ASSEMBLY SITE CODE

DAT E CODE YEAR 9 = 199 W EEK 1 6 LINE A

PRODUCT (OPTIONAL)

IRLR/U8113PbF

9

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

919A

78

PART NUMBER

DATE CODE YEAR 9 = 199 WE E K 19 LINE A

EXAMPLE:

THIS IS AN IRFU12 0 WIT H ASS E MB LY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE ASSE MBLY LINE "A"

Note: "P" in assembly line pos ition indicates "L ead-Free"

INTERNATIONAL

RECTIFIER

LOGO

AS S E MB LY LOT CODE

IRFU120

56

OR

INTERNATIONAL

RECTIFIER

LOGO

ASS E MB L Y LO T COD E

IRF U120

56 78

10 www.irf.com

PA RT NUMBER

DA TE CODE P = DE S I GNAT ES L E AD-F RE E

PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S I T E CODE

D-Pak (TO-252AA) Tape & Reel Information

TR

) )

N 1 2 3

Dimensions are shown in millimeters (inches)

TRR

IRLR/U8113PbF

TRL

12.1 ( .476 )

11.9 ( .469 )

OTES : . CONTROLLING DIMENSION : MILL IMETE R. . ALL DIMENSIONS ARE SHOW N IN MILLIMETERS ( INCHES ). . OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

I

AS

= 25°C, L = 1.8mH, RG = 25Ω,

J

= 13A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

16.3 ( .641 )

15.7 ( .619 )

FEED DIRECTION

16.3 ( .641

15.7 ( .619

8.1 ( .318 )

7.9 ( .312 )

16 mm

FEED DIRECTION

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 30A.

 When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.12/04

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