Datasheet irlr7833 Datasheet

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification for Telecom and Industrial Use

Benefits

l Very Low RDS(on) at 4.5V V l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage

GS

and Current

Absolute Maximum Ratings

Parameter Units

V

DS

V

GS

@ TC = 25°C

I

D

@ TC = 100°C

I

D

I

DM

PD @TC = 25°C

@TC = 100°C

P

D

T

J

T

STG

Drain-to-Source Voltage V

Gate-to-Source Voltage

Continuous Drain Current, V

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor W/°C Operating Junction and °C

Storage Temperature Range

Soldering Temperature, for 10 seconds

Mounting torque, 6-32 or M3 screw

c

@ 10V

GS

@ 10V

GS

g g

HEXFET® Power MOSFET

V

DSS

R

DS(on)

30V

D-Pak

IRLR7833

Max.

30

± 20

f

140

f

99

560

140

71

0.95

-55 to + 175

300 (1.6mm from case)

x

10 lbf

in (1.1Nxm)

IRLR7833 IRLU7833

max

4.5m

:

PD - 94547

Qg

33nC

I-Pak

IRLU7833

A

W

Thermal Resistance

Parameter Typ. Max. Units

R

θJC

R

θJA

R

θJA

Junct ion-to-Case ––– 1.05 Junct ion-to-Ambient (PCB Mount)

Junct ion-to-Ambient ––– 110

g

––– 50 °C/W

Notes  through  are on page 11

www.irf.com 1

11/26/02

IRLR/U7833

/

gy

(

)

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BV

DSS

∆Β

V

DSS

R

DS(on)

V

GS(th)

∆

V

GS(th)

I

DSS

I

GSS

gfs Forward Transconductance 66 ––– ––– S

Q

g

Q

gs1

Q

gs2

Q

gd

Q

godr

Q

sw

Q

oss

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

Avalanche Characteristics

E

AS

I

AR

E

AR

Diode Characteristics

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Drain-to-Source Breakdown Voltage 30 ––– ––– V

∆

T

Breakdown Voltage Temp. Coefficient ––– 19 ––– mV/°C

J

Static Drain-to-Source On-Resistance ––– 3.6 4.5

––– 4.4 5.5

Gate Threshold Voltage 1.5 ––– 2.2 V

∆

T

Gate Threshold Voltage Coefficient ––– -6.0 ––– mV/°C

J

Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 33 50

Pre-Vth Gate-to-Source Charge ––– 8.7 –––

Post-Vth Gate-to-Source Charge ––– 2.1 ––– nC

Gate-to-Drain Charge ––– 13 –––

Gate Charge Overdrive ––– 9.9 ––– See Fig. 16 Switch Charge (Q

gs2

+ Qgd)

––– 15 –––

Output Charge ––– 22 ––– nC

Turn-On Delay Time ––– 14 –––

Rise Time ––– 6.9 –––

Turn-Off Delay Time ––– 23 ––– ns

Fall Time ––– 15 –––

Input Capacitance ––– 4010 –––

Output Capacitance ––– 950 ––– pF

Reverse Transfer Capacitance ––– 470 –––

Parameter Units

Single Pulse Avalanche Ener

Avalanche Current

c

Repetitive Avalanche Energy

d

c

Typ.

–––

Parameter Min. Typ. Max. Units

f

Continuous Source Current ––– –––

(Body Diode) A Pulsed Source Current ––– ––– 560

Body Diode

ch

Diode Forward Voltage ––– ––– 1.0 V

Reverse Recovery Time ––– 39 58 ns

Reverse Recovery Charge ––– 37 55 nC

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

140

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, I

mΩ

V

= 10V, ID = 15A

GS

V

= 4.5V, ID = 12A

GS

VDS = VGS, ID = 250µA

V

= 24V, VGS = 0V

DS

V

= 24V, VGS = 0V, TJ = 125°C

DS

VGS = 20V

V

= -20V

GS

= 15V, ID = 12A

V

DS

= 16V

V

DS

= 4.5V

V

GS

I

= 12A

D

V

= 16V, VGS = 0V

DS

= 15V, VGS = 4.5V

V

DD

ID = 12A

Clamped Inductive Load

V

= 0V

GS

V

= 15V

DS

ƒ = 1.0MHz

Max.

530

20

14

Conditions

MOSFET symbol

showing the integral reverse

p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V

= 25°C, IF = 12A, VDD = 15V

T

J

di/dt = 100A/µs

f

= 1mA

D

f

G

mJ

A

mJ

D

S

f

2 www.irf.com

IRLR/U7833

1000

TOP 10V

)

100

A

( t n e

r

r u

C

10

e c

r u o S

-

1

o

t

n

i a

r D

,

0.1

D

I

2.25V

BOTTOM 2.25V

20µs PULSE WIDTH Tj = 25°C

0.01

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

1000.0

)

Α

(

t

100.00

n e

r

r u

C e

c

r

10.00

u o S

o

t

n

i a

r

1.00

D ,

D

I

TJ = 25°C

TJ = 175°C

V

= 25V

DS

20µs PULSE WIDTH

0.10

2.0 3.0 4.0 5.0 6.0

VGS, Gate-to-Source Voltage (V)

VGS

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

D

1000

100

TOP 10V

BOTTOM 2.25V

10

2.25V

20µs PULSE WIDTH

VGS

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

Tj = 175°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 30A

V

= 10V

GS

1.5

) d e z

i

l a

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

www.irf.com 3

IRLR/U7833

100000

) F

10000

p

( e c n a

t

i c a p a

C ,

1000

C

100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

C

iss

C

oss

C

rss

1 10 100

VDS, Drain-to-Source Voltage (V)

SHORTED

ds

gd

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

1000.00

) V

( e

g a

t

l o V

e c

r u o S

o

t

e

t a

G ,

S G

V

10000

6.0 ID= 12A

5.0

4.0

3.0

2.0

1.0

0.0

0 1020304050

VDS= 24V

VDS= 15V

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

OPERATION IN THIS AREA

) A

( t

100.00

n e

r

r u

C n

i a

r

10.00

D e

s

r e v e

R ,

1.00

D S

I

0.10

TJ = 175°C

TJ = 25°C

0.0 0.5 1.0 1.5 2.0 2.5

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode

V

GS

= 0V

) A

( t

1000

n e

r

r u

C e

c

r

100

u o S

o

t

n

i a

r D

10

,

Tc = 25°C

D

I

Tj = 175°C Single Pulse

1

1 10 100 1000

Fig 8. Maximum Safe Operating Area

LIMITED BY RDS(on)

100µsec

1msec

10msec

VDS, Drain-to-Source Voltage (V)

Forward Voltage

4 www.irf.com

IRLR/U7833

150

LIMITED BY PACKAGE

125

100

75

50

D

I , Drain Current (A)

25

0

25 50 75 100 125 150 175

TC, Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

Case Temperature

10

2.5

) V

( e

2.0

g a

t

l o V

d

l

1.5

o h s e

r h

t

1.0

e

t a

G

) h

t

(

0.5

S G

V

0.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage vs. Temperature

thJC

1

D = 0.50

0.20

P

1 2

DM

t

1

t

2

0.10

0.1

0.05

0.02

Thermal Response (Z )

0.01

0.00001 0.0001 0.001 0.01 0.1 1

SINGLE PULSE

(THERMAL RESPONSE)

t , Rectangular Pulse Duration (sec)

1

Not es:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJC C

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRLR/U7833

A

+

-

15V

V

DS

R

G

20V

V

GS

L

D.U.T

I

AS

Ω

0.01

t

p

DRIVER

+

V

DD

-

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

Current Regulator

Same Type as D.U.T.

50KΩ

12V

.2µF

.3µF

D.U.T.

+

V

DS

-

15000

) J

m

( y

12500

g

r e n E

e

10000

h c n a

l a

7500

v A

e s

l u

5000

P e

l g n

i S

2500

,

S A

E

0

25 50 75 100 125 150

TOP 8.2A

BOTTOM20A

Starting TJ , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

R

V

DS

V

GS

R

G

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

D

D.U.T.

Fig 14a. Switching Time Test Circuit

V

DS

90%

I

D

14A

V

DD

V

GS

3mA

10%

I

G

Current Sampling Resistors

I

D

Fig 13. Gate Charge Test Circuit

V

GS

t

d(on)tr

t

d(off)tf

Fig 14b. Switching Time Waveforms

6 www.irf.com

IRLR/U7833

+

-

Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

D.U.T

+



-

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

+



V

DD

R

G

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

Re-Applied Voltage

Inductor Curent

* V

GS

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

www.irf.com 7

IRLR/U7833

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

 

+ I ×



+ Q

()

Q



+



This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

× Vg× f

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

 



 

and Q

gs1

+ P

+ I ×

+ P

drive



Q

gs 2



i



g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin× f

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

= P

loss

conduction

P

= I

loss

+ Qg× Vg× f

+

rms

()

 



*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

 

portance of gate charge must not be overlooked since



it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

Q

oss

×Vin× f

2

gs1

Characteristic

oss

drive

must be minimized to reduce the

+ P

 

*

output

+ Q

(

× Vin× f

rr

ds(on)

oss

is an im-

and re-

8 www.irf.com

TO-252AA (D-Pak) Package Outline

,17(51$7,21$/

/

2*2

5(&7,),(5









,5)8



$

/27&2'

(

$66(0%/

<

(;$

03/(

:,7

+$66(0%/

<

7+,

6

,6$1,5)5



<($

5 



'$7(&2'(

/,1(

$

:((.

,17+($66(0%/</,1($



$66(0%/('21::







/27&2'(

3$57180%(5

Dimensions are shown in millimeters (inches)

IRLR/U7833

5.46 (.215 )

5.21 (.205 )

1.02 (.040)

1.64 (.025)

1.52 (.060)

1.15 (.045)

1.14 (.045)

2X

0.76 (.030)

2.28 (.090)

6.73 (.265)

6.35 (.250)

- A -

4

1 2 3

1.27 (.050 )

0.88 (.035 )

6.22 (.245)

5.97 (.235)

- B -

0.89 (.035)

3X

0.64 (.025)

0.25 (.010) M A M B

4.57 (.180)

2.38 (.094)

2.19 (.086)

10.42 (.410)

9.40 (.37 0)

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JE DEC OUTLINE TO-252AA.

4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,

SOLD ER DIP MAX. +0. 16 (.0 06).

1.14 (.045)

0.89 (.035)

0.58 (.02 3)

0.46 (.01 8)

6.45 (.245)

5.68 (.224)

0.51 (.02 0) MIN.

0.58 (.023)

0.46 (.018)

LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE 4 - DRAIN

TO-252AA (D-Pak) Part Marking Information

www.irf.com 9

IRLR/U7833

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

5.46 (.215)

5.21 (.205)

1.52 (.060)

1.15 (.045)

- B -

2.28 (.090)

1.91 (.075)

1.14 (.045)

3X

0.76 (.030)

2.28 (.090)

6.73 (.265)

6.35 (.250)

- A -

4

1 2 3

3X

2X

1.27 (.050)

0.88 (.035)

6.22 (.245)

5.97 (.235)

9.65 (.380)

8.89 (.350)

0.89 (.035)

0.64 (.025)

0.25 (.010) M A M B

2.38 (.094)

2.19 (.086)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH.

3 C ONFORMS TO J EDEC OUTLINE TO-25 2AA.

4 D IMENSION S SHOW N ARE BEF ORE SOLDER DIP,

SOLDER DIP MAX. +0.16 (.006).

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

I-Pak (TO-251AA) Part Marking Information

LEAD ASSIGNMENTS

1 - GATE 2 - DRAIN

3 - SOURCE

4 - DRAIN

10 www.irf.com

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRR

IRLR/U7833

TRL

12.1 ( .47 6 )

11.9 ( .46 9 )

NOTES :

1. CONTROLLIN G DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

FEED DIRECT ION

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting T

I

AS

= 25°C, L = 2.6mH, RG = 25Ω,

J

= 20A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

8.1 ( .318 )

7.9 ( .312 )

16 mm

FEED DIRECTION

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 30A.

 When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.11/02

www.irf.com 11