Datasheet IRLR3705ZTRPBF Specification

Page 1
PD - 95956A
IRLR3705ZPbF
Features
l
Logic Level
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
175°C Operating Temperature
l
Fast Switching
l
Repetitive Avalanche Allowed up to Tjmax
l
Lead-Free
Description
This HEXFET® Power MOSFET utilizes the latest
G
IRLU3705ZPbF
HEXFET® Power MOSFET
D
= 55V
DSS
R
S
DS(on)
ID = 42A
= 8.0mΩ
processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications.
D-Pak
IRLR3705ZPbF
I-Pak
IRLU3705ZPbF
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
@ TC = 25°C
I
D
I
DM
PD @TC = 25°C
V
GS
E
AS (Th ermally limited)
E
(Tested )
AS
I
AR
E
AR
T
J
T
STG
Parameter Units
(Silicon Limited)
Continuous Drain Current, V
Continuous Drain Current, V
Continuous Drain Current, V Pulsed Drain Current
Power Dissipation W
Linear Derating Factor W/°C Gate-to-S ource Voltage V
Single Pulse Avalanche Energy
Single P ulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Operating Junction and
Storage Temperature Range °C
Soldering Tem perature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
c
c
@ 10V
GS
@ 10V
GS
@ 10V
GS
d
g
(Package Limited)
h
See Fig.12a, 12b, 15, 16
300 (1.6mm from case )
Max.
89
63
42
360
130
0.88
± 16
110
190
-55 to + 175
10 lbf
y
in (1.1Nym)
A
mJ
A
mJ
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
JA
θ
R
θJA
Junction-to-Case
Junction-to-Ambient (PCB mount)
Junction-to-Ambient
j
ij
j
––– 1.14
––– 40 °C/W
––– 110
HEXFET® is a registered trademark of International Rectifier.
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10/01/10
Page 2
IRLR/U3705ZPbF
ified)
Electrical Characteristics @ TJ = 25°C (unless otherwise spec
Parameter Min. Typ. Max. Units
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
gfs Forward Transconductance 89 ––– ––– S
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
oss
C
oss
eff. Effective Output Capacitance ––– 500 –––
C
oss
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Drain-to-Source Breakdown Voltage 55 ––– ––– V
/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.053 ––– V/°C
Static Drain-to-S ource On-Resistance ––– 6.5 8.0
––– ––– 11
––– ––– 12
Gate Threshold Voltage 1.0 ––– 3.0 V
Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
Total Gate Charge ––– 44 66
Gate-to-Source Charge ––– 13 ––– nC
Gate-to-Drain ("Miller") Charge ––– 22 –––
Turn-On Delay Time ––– 17 –––
Rise Time ––– 150 –––
Turn-Off Delay Time ––– 33 ––– ns
Fall Time –––70–––
Internal Drain Inductance ––– 4.5 ––– Between lead,
Internal Source Inductance ––– 7.5 ––– from package
Input Capacitance ––– 2900 –––
Output Capacitance ––– 420 –––
Reverse Transfer Capacitance ––– 230 ––– pF
Output Capacitance ––– 1550 –––
Output Capacitance ––– 320 –––
Parameter Min. Typ. Max. Units
Continuous Source Current ––– ––– 42
(Body Diode) A Pulsed Source Current ––– ––– 360
(Body Diode) Diode Forward Voltage ––– ––– 1.3 V
Reverse Recovery Time ––– 21 42 ns
Reverse Recovery Charge ––– 14 28 nC
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
c
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, I
Ω
m
VGS = 10V, ID = 42A
VGS = 5.0V, ID = 34A
= 4.5V, ID = 21A
V
GS
= VGS, ID = 250µA
V
DS
V
= 25V, ID = 42A
DS
V
= 55V, VGS = 0V
DS
V
= 55V, VGS = 0V, TJ = 125°C
DS
VGS = 16V
V
= -16V
GS
= 42A
I
D
= 44V
V
DS
VGS = 5.0V
e
VDD = 28V
= 42A
I
D
= 4.2
G
Ω
e
R
VGS = 5.0V
nH 6mm (0.25in.)
and center of die contact
VGS = 0V
= 25V
V
DS
ƒ = 1.0MHz
V
= 0V, VDS = 1.0V, ƒ = 1.0MHz
GS
V
= 0V, VDS = 44V, ƒ = 1.0MHz
GS
= 0V, VDS = 0V to 44V
V
GS
Conditions
MOSFET symbol
showing the integral reverse
p-n junction diode. T
= 25°C, IS = 42A, VGS = 0V
J
TJ = 25°C, IF = 42A, VDD = 28V
di/dt = 100A/µs
e
= 1mA
D
e
e e
D
G
S
f
e
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Page 3
IRLR/U3705ZPbF
1000
) A
( t n e
r
r
100
u C e
c
r u o S
­o
t
­n
10
i a
r D
,
D
I
2.8V
≤
TOP 12V
BOTTOM 2.8V
60µs PULSE WIDTH
Tj = 25°C
1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
1000.0
)
Α
(
t n e
r
r
100.0
u C e
c
r u o S
­o
t
­n
i a
r D
,
D
I
10.0
TJ = 25°C
V
= 15V
DS
≤ 60µs PULSE WIDTH
1.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate-to-Source Voltage (V)
VGS
10V
8.0V
5.0V
4.5V
3.5V
3.0V
TJ = 175°C
1000
) A
( t n e
r
r u
C e
c
r u o S
­o
t
­n
i a
r D
,
D
I
TOP 12V
100
BOTTOM 2.8V
10
VGS
10V
8.0V
5.0V
4.5V
3.5V
3.0V
2.8V
60µs PULSE WIDTH
≤
Tj = 175°C
1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
100
) S
( e
80
c n a
t c u d n
60
o c s n a
r T
40
d
r a
w
r o F ,
20
s
f G
V
380µs PULSE WIDTH
0
0 1020304050607080
ID, Drain-to-Source Current (A)
DS
TJ = 25°C
TJ = 175°C
= 8.0V
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
vs. Drain Current
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Page 4
IRLR/U3705ZPbF
5000
4000
) F p
( e
3000
c n a
t
i c a p
2000
a C
, C
1000
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
oss
= C
gd
ds
C
Ciss
+ Cgd, C
+ C
Coss
Crss
0
1 10 100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000.0
) A
( t
100.0
n e
r
r u
C n
i a
r D e
s
r e v e
R ,
D S
I
TJ = 175°C
10.0
TJ = 25°C
1.0
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
12
SHORTED
ds
gd
ID= 42A
) V
(
10
e g a
t
l o
8
V e
c
r u o
6
S
­o
t
­e
t
4
a G
,
S G
2
V
VDS= 44V VDS= 28V
VDS= 11V
0
0 20406080100
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
V
GS
= 0V
10000
) A
(
1000
t n e
r
r u
C
100
e c
r u o S
­o
t
10
­n
i a
r D ,
1
D
I
Tc = 25°C Tj = 175°C Single Pulse
0.1 1 10 100
OPERATION IN THIS AREA LIMITED BY RDS(on)
1msec
10msec
DC
V
, Drain-toSource Voltage (V)
DS
100µsec
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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Page 5
IRLR/U3705ZPbF
τ
100
LIMITED BY PACKAGE
80
) A
( t n e
60
r
r u
C n
i a
r
40
D ,
D
I
20
0
25 50 75 100 125 150 175
TC , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
10
2.5
e c n a
t s
i s e
R n O
)
e
d
c
r
e
u
z
i
l
o
a
S
-
m
o
r
t
-
o
n
i
N
(
a
r D
,
) n o
( S D
R
ID = 42A
V
= 10V
GS
2.0
1.5
1.0
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
)
C
1
J h
t Z (
e s n o p s e
R l a
m
r e h T
0.001
D = 0.50
0.20
0.1
0.10
0.05
τ
J
0.02
0.01
0.01
SINGLE PULSE ( THERMAL RESPONSE )
1E-006 1E-005 0.0001 0.001 0.01 0.1
τ
J
τ
1
Ci= τi/Ri
R
R
1
2
R
R
1
2
τ
τ
1
2
τ
2
Ri (°C/W) τi (sec)
τ
C
0.6984 0.000465
0.4415 0.004358
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRLR/U3705ZPbF
A
15V
L
D.U.T
I
AS
Ω
0.01
t
p
R
20V
V
V
DS
G
GS
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
DRIVER
+
-
V
DD
500
) J
m
( y
g
r
400
e n E
e h c
300
n a
l a v A
e s
200
l u P
e
l g n
i
100
S
, S A
E
0
25 50 75 100 125 150 175
I
TOP
7.0A
BOTTOM
Starting TJ, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
D
5.3A
42A
10 V
Q
GS
V
G
Fig 13a. Basic Gate Charge Waveform
0
1K
Fig 13b. Gate Charge Test Circuit
Q
GD
Charge
DUT
2.5
) V
( e
2.0
g a
t
l o V
d
l
1.5
o h s e
r h
t e
1.0
t a
G ) h
t
(
S
0.5
L
G
V
ID = 250µA
ID = 150µA
ID = 50µA
VCC
0.0
-75 -50 -25 0 25 50 75 100 125 150 175
TJ , Temperature ( °C )
Fig 14. Threshold Voltage vs. Temperature
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Page 7
IRLR/U3705ZPbF
1000
Duty Cycle = Single Pulse
100
)
A
(
t
n
e
r
r
u
C
10
e
h
c
n
a
l
a
v
A
1
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
0.01
0.05
0.10
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆Tj = 25°C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax
120
TOP Single Pulse
)
100
J m
( y
g
r
80
e n E
e h
60
c n a
l a v
40
A ,
R A
E
20
BOTTOM 1% Duty Cycle ID = 42A
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T every part type.
2. Safe operation in Avalanche is allowed as long asT not exceeded.
. This is validated for
jmax
jmax
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
avalanche pulse.
= Average power dissipation per single
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceed
T
(assumed as 25°C in Figure 15, 16).
0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
jmax
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t Z
(D, tav) = Transient thermal resistance, see figure 11)
thJC
P
= 1/2 ( 1.3·BV·Iav) = DT/ Z
D (ave)
I
2DT/ [1.3·BV·Zth]
av =
E
AS (AR)
= P
·f
av
D (ave)·tav
thJC
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is
Page 8
IRLR/U3705ZPbF
Reverse Recovery Current
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance Current Transformer
-
• dv/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied Voltage
+
-
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
R
D.U.T.
D
+
V
DD
-
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
t
d(off)tf
Fig 18b. Switching Time Waveforms
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Page 9
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
IRLR/U3705ZPbF
D-Pak (TO-252AA) Part Marking Information
EXAMPL E:
THIS IS AN IRFR120 WIT H AS SE MB LY LOT CODE 1234 AS SE MB LED ON WW 16, 2001 IN THE ASS EMBLY LINE "A"
Note: "P" in ass embly line pos ition
in dicates "L ead-F r ee"
"P" in assembly line position indicates "L ead-F ree" q uali fi cati on to the cons umer -l evel
OR
INTERNATIONAL
RECTIFIER
LOGO
AS S E MB L Y LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
AS S E MB L Y LOT CODE
IRF R120
12
IRF R120
PART NUMBER
DATE CODE P = DESIGNAT ES L EAD-FRE E
34
P = DESIGNAT ES L EAD-FRE E
YEAR 1 = 2001 WE E K 16 A = AS S E MB L Y S I T E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com 9
PART NUMBER
DATE CODE
116A
YEAR 1 = 2001
3412
WE EK 16 LINE A
PRODUCT (OPTIONAL )
PRODUCT QUALIFIED TO THE CONS UME R LEVEL (OPTI ONAL)
Page 10
IRLR/U3705ZPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE :
THIS IS AN IRF U120 WI T H AS S EM BL Y LOT CODE 5678 ASS EMBLED ON WW 19, 2001 IN T HE ASSEMBLY LINE "A"
Note: "P" in assembly line position
in dicates L ead- F ree"
INTERNATIONAL
RECTIFIER
LOGO
AS S E MB L Y LOT CODE
IRFU120
56
OR
INTERNATIONAL
RECTIFIER
LOGO
AS S E MB L Y LOT CODE
IRFU 120
56 78
PART NUMBER
DATE COD E P = DES IGNATES LEAD-FREE
YEAR 1 = 2001 WE E K 1 9 A = ASSEMBLY SITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10 www.irf.com
PART NUMBER
DATE CODE
119A
PRODUCT (OPT IONAL)
YEAR 1 = 2001
78
WE E K 1 9 LINE A
Page 11
IRLR/U3705ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters
TR
TRR TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMET ERS ( INCHES ).
3. OUTLINE CONFO RMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
FEED DIRECTION
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
 Limited by T
RG = 25Ω, I
, starting TJ = 25°C, L = 0.12mH
Jmax
= 42A, VGS =10V. Part not
AS
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
C
eff. is a fixed capacitance that gives the same charging time
oss
as C Limited by T
16 mm
oss
FEED DIR ECTION
while V
is rising from 0 to 80% V
DS
, see Fig.12a, 12b, 15, 16 for typical repetitive
Jmax
DSS
.
avalanche performance. This value determined from sample failure population. 100% tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
R
is measured at TJ approximately 90°C
θ
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/2010
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