Page 1
PD - 95087A
IRLR/U3410PbF
l Logic Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR3410)
l Straight Lead (IRLU3410)
l Advanced Process Technology
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
G
HEXFET® Power MOSFET
D
V
= 100V
DSS
R
DS(on)
= 0.105Ω
ID = 17A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
D-PAK
TO-252AA
I-PAK
TO-251AA
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 17
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 12 A
I
DM
PD @TC = 25°C Power Dissipation 79 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
T
J
T
STG
Pulsed Drain Current 60
Linear Derating Factor 0.53 W/°C
Gate-to-Source Voltage ± 16 V
Single Pulse Avalanche Energy 150 mJ
Avalanche Current 9.0 A
Repetitive Avalanche Energy 7.9 mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
R
θJA
Junction-to-Case ––– 1.9
Junction-to-Ambient (PCB mount) ** ––– 50 °C/W
Junction-to-Ambient ––– 110
www.irf.com 1
12/7/04
Page 2
IRLR/U3410PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
RG = 25Ω, I
I
SD
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2 www.irf.com
Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.122 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance
––– ––– 0.105 V
––– ––– 0.125 W VGS = 5.0V, ID = 10A
= 10V, ID = 10A
GS
––– ––– 0.155 VGS = 4.0V, ID = 9.0A
Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
Forward Transconductance 7.7 ––– ––– S VDS = 25V, ID = 9.0A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
µA
nA
V
= 100V, VGS = 0V
DS
VGS = 16V
Total Gate Charge ––– ––– 34 ID = 9.0A
Gate-to-Source Charge ––– ––– 4.8 nC VDS = 80V
Gate-to-Drain ("Miller") Charge ––– ––– 20 VGS = 5.0V, See Fig. 6 and 13
Turn-On Delay Time ––– 7.2 ––– VDD = 50V
Rise Time ––– 53 –––
Turn-Off Delay Time ––– 30 ––– RG = 6.0Ω, VGS = 5.0V
ns
ID = 9.0A
Fall Time ––– 26 ––– RD = 5.5Ω, See Fig. 10
Internal Drain Inductance 4.5
Internal Source Inductance ––– 7.5 –––
Between lead,
nH
6mm (0.25in.)
from package
and center of die contact
Input Capacitance ––– 800 ––– VGS = 0V
Output Capacitance ––– 160 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 90 ––– ƒ = 1.0MHz, See Fig. 5
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
17
60
showing the
A
p-n junction diode.
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 9.0A, VGS = 0V
Reverse Recovery Time ––– 140 210 ns TJ = 25°C, IF =9.0A
Reverse RecoveryCharge ––– 740 1100 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%
= 25V, starting TJ = 25°C, L = 3.1mH
= 9.0A. (See Figure 12)
AS
≤ 9.0A, di/dt ≤ 540A/µs, V
DD
≤ V
(BR)DSS
Uses IRL530N data and test conditions
,
This is applied for I-PAK, L
center of die contact
of D-PAK is measured between lead and
S
G
G
D
S
D
S
Page 3
IRLR/U3410PbF
A
A
A
A
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
1
D
I , Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
T = 25°C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 1. Typical Output Characteristics
100
T = 25°C
J
T = 175°C
J
10
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
2.5V
1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
T = 175°C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output Characteristics
3.0
I = 15A
D
2.5
2.0
1.5
(Normalized)
1
D
I , Drain-to-Source Current (A)
0.1
2345678910
V , Gate-to-Source Voltage (V)
GS
V = 50V
DS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperat ure (°C)
J
Fig 4. Normalized On-Resistance
V = 10V
GS
Vs. Temperature
www.irf.com 3
Page 4
IRLR/U3410PbF
A
A
A
A
1400
1200
1000
800
600
C, Capacitance (pF)
400
200
0
1 10 100
V = 0V, f = 1MHz
GS
C = C + C , C SHORTED
iss gs gd ds
C = C
rss gd
C = C + C
oss ds gd
C
iss
C
oss
C
rss
V , Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
15
I = 9.0A
D
12
9
6
3
GS
V , Gate-to-Source Voltage (V)
V = 80V
DS
V = 50V
DS
V = 20V
DS
FOR TEST CIRCUIT
0
0 1020304050
Q , Total Gate Charge (nC)
G
SEE FIGURE 13
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T = 175°C
J
10
SD
I , Reverse Drain Current (A)
1
0.4 0.6 0.8 1.0 1.2 1.4
V , Source-to-Drain Voltage (V)
SD
T = 25°C
J
V = 0V
Fig 7. Typical Source-Drain Diode
GS
100
10µs
10
D
I , Drain Current (A)
T = 25°C
C
T = 175°C
J
Single Pulse
1
1 10 100 1000
V , Drain-to-Source Voltage (V)
DS
100µs
1ms
10ms
Fig 8. Maximum Safe Operating Area
Forward Voltage
4 www.irf.com
Page 5
IRLR/U3410PbF
20
15
10
D
I , Drain Current (A)
5
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
D
D.U.T.
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
thJC
D = 0.50
1
0.20
0.10
P
1 2
DM
t
1
t
2
0.05
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com 5
Page 6
IRLR/U3410PbF
A
A
15V
V
DS
R
G
10V
t
L
D.U.T
I
AS
Ω
0.01
p
DRIVER
+
-
V
DD
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
350
300
250
200
150
100
50
AS
V = 25V
E , Single Pulse Avalanche Energy (mJ)
DD
0
25 50 75 100 125 150 175
Starting T , Junction Temperature (°C)
J
I
TOP 3.7A
6.4A
BOTTOM 9.0A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
D
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
5.0 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
+
D
Fig 13b. Gate Charge Test Circuit
V
DS
-
6 www.irf.com
Page 7
IRLR/U3410PbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFETS
www.irf.com 7
Page 8
IRLR/U3410PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE:
Note: "P" in assembly line position
8 www.irf.com
T HIS IS AN IRF R120
WIT H AS S EMB L Y
LOT CODE 1234
ASS EMBLE D ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
i ndi cates "L ead-F r ee"
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
IRFU120
12 34
PART NUMBER
IRF U120
916A
12
34
PART NUMBER
DATE CODE
P = DE S I GN AT E S LE AD- F R E E
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WE E K 1 6
A = ASSEMBLY SITE CODE
DATE CODE
YEAR 9 = 1999
WE E K 1 6
LINE A
Page 9
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
IRLR/U3410PbF
I-Pak (TO-251AA) Part Marking Information
EXAMPLE:
THIS IS AN IRFU120
WITH ASSEMBLY
LOT CODE 5678
ASS E MBLE D ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
Note: "P" in ass embly line
position indicates "Lead-Free"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
IRF U120
56
919A
78
OR
INTE RNATIONAL
RECTIF IER
LOGO
ASSEMBLY
LOT CODE
IRFU 120
56 78
www.irf.com 9
PART NUMBER
DAT E CODE
P = D E S IGN AT ES L E AD- F R E E
PRODUCT (OPTIONAL )
YEAR 9 = 1999
WE E K 19
A = ASSEMBLY SITE CODE
PART NUMBER
DATE CODE
YEAR 9 = 1999
WEEK 19
LINE A
Page 10
IRLR/U3410PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .47 6 )
11.9 ( .46 9 )
NOTES :
1. CONTROLL ING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OU TLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
FEED DIRECTION
8.1 ( .318 )
7.9 ( .312 )
16 mm
16.3 ( .641 )
15.7 ( .619 )
FEED DIRECTION
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10 www.irf.com
Page 11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
Loading...