Datasheet IRLR2705PBF Specification

PD- 91317C

IRLR/U2705

HEXFET® Power MOSFET

l Logic-Level Gate Drive l Ultra Low On-Resistance l Surface Mount (IRLR2705) l Straight Lead (IRLU2705) l Advanced Process Technology l Fast Switching l Fully Avalanche Rated

G

D

V

= 55V

DSS

R

DS(on)

= 0.040Ω

ID = 28A

S

Description

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications.

The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for

D-Pak TO-252AA

I-Pak TO-251AA

through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 28 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 20 A I

DM

PD @TC = 25°C Power Dissipation 68 W

V

GS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt  5.0 V/ns T

J

T

STG

Pulsed Drain Current  110

Linear Derating Factor 0.45 W/°C Gate-to-Source Voltage ± 16 V Single Pulse Avalanche Energy 110 mJ Avalanche Current 16 A Repetitive Avalanche Energy 6.8 mJ

Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Thermal Resistance

Parameter Typ. Max. Units

R

θJC

R

θJA

R

θJA

** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994

Junction-to-Case ––– 2.2 Case-to-Ambient (PCB mount)** ––– 50 °C/W Junction-to-Ambient ––– 110

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4/1/03

IRLR/U2705

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

∆V

R

DS(on)

V

GS(th)

g

fs

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

(BR)DSS

Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.065 ––– V/°C Reference to 25°C, ID = 1mA

J

––– ––– 0.040 VGS = 10V, ID = 17A 

Static Drain-to-Source On-Resistance

––– ––– 0.051 W VGS = 5.0V, ID = 17A 

––– ––– 0.065 VGS = 4.0V, ID = 14A  Gate Threshold Voltage 1.0 ––– 2 .0 V VDS = VGS, ID = 250µA Forward Transconductance 11 –– – ––– S VDS = 25V, ID = 16A

Drain-to-Source Leakage Current

––– ––– 25

––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V

VDS = 55V, VGS = 0V

µA

VGS = 16V

nA

Total Gate Charge ––– ––– 25 ID = 16A Gate-to-Source Charge ––– ––– 5.2 nC VDS = 44V Gate-to-Drain ("Miller") Charge ––– ––– 14 VGS = 5.0V, See Fig. 6 and 13  Turn-On Delay Time ––– 8.9 – –– VDD = 28V Rise Time ––– 100 ––– Turn-Off Delay Time ––– 21 –– – RG = 6.5Ω, VGS = 5.0V

ns

ID = 16A

Fall Time ––– 29 ––– RD = 1.8Ω, See Fig. 10  Internal Drain Inductance  4.5 

Internal Source Inductance ––– 7.5 –– –

Between lead,

nH

6mm (0.25in.) from package

and center of die contact Input Capacitance ––– 880 ––– VGS = 0V Output Capacitance ––– 220 ––– pF VDS = 25V Reverse Transfer Capacitance –– – 94 ––– ƒ = 1.0MHz, See Fig. 5

D

G

S

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode) 

––– –––

28

110

showing the

A

p-n junction diode.

G

Diode Forward Voltage –– – ––– 1.3 V TJ = 25°C, IS = 17A, VGS = 0V  Reverse Recovery Time ––– 76 110 ns TJ = 25°C, IF = 16A Reverse RecoveryCharge ––– 190 290 nC di/dt = 100A/µs



Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

 V

= 25V, starting TJ = 25°C, L = 610µH

DD

RG = 25Ω, I

 I

≤ 16A, di/dt ≤ 270A/µs, V

SD

= 16A. (See Figure 12)

AS

DD

≤ V

(BR)DSS

,

 Caculated continuous current based on maximum allowable

junction temperature; Package limitation current = 20A.

 This is applied for I-PAK, L

of D-PAK is measured between

S

lead and center of die contact.

 Uses IRLZ34N data and test conditions.

TJ ≤ 175°C

 Pulse width ≤ 300µs; duty cycle ≤ 2%.

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D

S

IRLR/U2705

A

1000

VGS TOP 15V 12V 10V

8.0V

6.0V

4.0V

3.0V

100

BOTTOM 2.5V

10

1

D

I , Drain-to-Source Current (A)

2.5V

20µs PULSE WIDTH T = 25°C

0.1

0.1 1 10 100

V , Drain-to-Source Voltage (V)

DS

1000

J

1000

VGS TOP 15V 12V 10V

8.0V

6.0V

4.0V

3.0V

100

BOTTOM 2.5V

10

2.5V

1

D

I , Drain-to-Source Current (A)

20µs PULSE WIDTH T = 175°C

0.1

0.1 1 10 100

V , Drain-to-Source Voltage (V)

DS

J

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

3.0

I = 27A

D

2.5

100

10

1

D

I , Drain-to-Source Current (A)

0.1 2345678910

Fig 3. Typical Transfer Characteristics

T = 25°C

J

T = 175°C

J

V = 25V

DS

20µs PULSE WIDTH

V , Gate-to-So urc e Voltage (V)

GS

2.0

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

T , Junction Temperature (°C)

J

Fig 4. Normalized On-Resistance

V = 10V

GS

Vs. Temperature

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IRLR/U2705

A

1400

1200

1000

800

600

C, Capacitance (pF)

400

200

0

1 10 100

V = 0V, f = 1MHz

GS

C = C + C , C SHORTED

iss gs gd ds

C = C

rss gd

C = C + C

C

oss ds gd

iss

C

oss

C

rss

V , Drain-to-Source Voltage (V)

DS

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000

15

I = 16A

D

V = 44V

DS

12

9

6

3

GS

V , Gate-to-Source Voltage (V)

V = 28V

DS

FOR TEST CIRCUIT

0

0 4 8 121620242832

Q , Total Gate Charge (nC)

G

SEE FIGUR E 13

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

OPERATION IN THIS AREA LIMITED BY R

DS(on)

100

T = 175°C

J

T = 25°C

10

SD

I , Reverse Drain Current ( A )

1

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V , Source-to-Drain Voltage (V)

SD

J

V = 0V

Fig 7. Typical Source-Drain Diode

GS

100

10

D

I , Drain Current (A)

T = 25°C

C

T = 175°C

J

Single Pulse

1

1 10 100

V , Drain-to-Source Voltage (V)

DS

Fig 8. Maximum Safe Operating Area

10µs

100µs

1ms

10ms

Forward Voltage

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IRLR/U2705

R

D.U.T.

D

+

V

DD

-

30

LIMITED BY PACKAGE

25

R

20

V

DS

V

GS

G

5V

15

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

10

D

I , Drain Current (A)

5

Fig 10a. Switching Time Test Circuit

V

DS

90%

0

25 50 75 100 125 150 175

T , Case Temperature ( C)

C

°

10% V

GS

Fig 9. Maximum Drain Current Vs.

t

d(on)tr

t

d(off)tf

Case Temperature

Fig 10b. Switching Time Waveforms

10

thJC

D = 0.50

1

0.20

0.10

0.05

0.1

0.02

0.01

SINGLE PULSE

(THERMAL RESPONSE)

Thermal Response (Z )

Notes:

1. Duty factor D = t / t

2. Peak T =P x Z + T

0.01

0.00001 0.0001 0.001 0.01 0.1

t , Rectangular Pulse Duration (sec)

1

J DM thJC C

1 2

P

DM

t

1

t

2

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U2705

A

15V

DRIVER

+

-

R

20V

V

DS

G

t

L

D.U.T

I

AS

Ω

0.01

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

250

200

150

V

DD

100

50

AS

V = 25V

E , Single Pulse Avalanche Energy (mJ)

DD

0

25 50 75 100 125 150 175

Starting T , Junction Temperature (°C)

J

I TOP 6.6A 11A BOTTOM 16A

D

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

10 V

Q

GS

V

G

Q

GD

Charge

Fig 13a. Basic Gate Charge Waveform

Current Regulator

Same Type as D.U.T.

50KΩ

12V

.2µF

V

GS

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

I

+

-

D

Fig 13b. Gate Charge Test Circuit

V

DS

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IRLR/U2705

Peak Diode Recovery dv/dt Test Circuit



D.U.T

+



-

R

G

Driver Gate Drive

P.W.

+

Circuit Layout Considerations

• Low Stray Inductance



• Ground Plane

• Low Leakage Inductance Current Transformer

-

• dv/dt controlled by R

G

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

Period

D =



P.W.

Period

+

V

DD

-

VGS=10V

*

D.U.T. ISDWaveform

Reverse Recovery Current

Re-Applied Voltage

D.U.T. VDSWaveform

Inductor Curent

* V

= 5V for Logic Level Devices

GS

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

V

DD

I

SD

Fig 14. For N-Channel HEXFETS

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IRLR/U2705

A

Package Outline

TO-252AA Outline

Dimensions are shown in millimeters (inches)

6.73 (.265)

6.35 (.250)

- A -

5.46 (.215)

5.21 (.205) 4

6.22 (.245)

1.02 (.040)

1.64 (.025)

1.52 (.060)

1.15 (.045)

1.14 (.045)

2X

0.76 (.030)

2.28 (.090)

1 2 3

5.97 (.235)

0.89 (.035)

3X

0.64 (.025)

0.25 (.010) M A M B

4.57 (.180)

Part Marking Information

TO-252AA (D-PARK)

- B -

1.27 (.050)

0.88 (.035)

2.38 (.094)

2.19 (.086)

10.42 (.410)

9.40 (.370)

NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLI NG DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DI P MAX. +0.16 (.006).

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

0.51 (.020) MIN.

0.58 (.023)

0.46 (.018)

LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

EXAMPLE : THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P

INTERNATIONAL RECTIFIER LOGO

IRFR

120

FIRST PORTION OF PART NUMBER

9U 1P ASSEMBLY LOT CODE

SECOND PORTION OF PART NUMBER

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Package Outline

R

N

TO-251AA Outline

Dimensions are shown in millimeters (inches)

IRLR/U2705

6.73 (.265)

6.35 (.250)

5.46 (.215)

5.21 (.205)

1.52 (.060)

1.15 (.045)

- B -

2.28 (.090)

1.91 (.075)

1.14 (.04 5 )

3X

0.76 (.03 0 )

2.28 (.090)

- A -

4

1 2 3

3X

2X

1.27 (.05 0 )

0.88 (.03 5 )

6.22 (.245)

5.97 (.235)

9.65 (.380)

8.89 (.350)

0.89 (.035)

0.64 (.025)

0.25 (.010) M A M B

Part Marking Information

TO-251AA (I-PARK)

2.38 (.094)

2.19 (.086)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

NOTES: 1 DIMENSI O NING & TOLERANCI NG PER ANS I Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSI O NS SH O WN ARE BEFORE SO L DER DIP, SOLDER DIP MAX. +0.16 (.006).

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

LEAD ASSI GNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

EXAMPLE : THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 9U1P

INTERNATIONAL RECTIFIER LOGO

IRFU

120

FIRST PORTION OF PART NUMBE

9U 1P ASSEMBLY LOT CODE

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SECOND PORTIO OF PART NUMBER

IRLR/U2705

Tape & Reel Information

TO-252AA

Dimensions are shown in millimeters (inches)

TR

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

NOTES :

1. CONTROLLING DIM ENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

FEED DIRECTION

8.1 ( .318 )

7.9 ( .312 )

TRR

TRL

16.3 ( .641 )

15.7 ( .619 )

FEED DIRECTION

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

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IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897

IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086

IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371

IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590

IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111

http://www.irf.com/ Data and specifications subject to change without notice. 4/03

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