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PD - 94390
IRLI3615
HEXFET® Power MOSFET
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
G
D
V
= 150V
DSS
R
S
= 0.085 Ω
DS(on)
ID = 14A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and ruggedized device
design that HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for use in a wide variety
of applications.
The TO-220 Fullpak eliminates the need for additional insulating hardware in
commercial-industrial applications. The moulding compound used provides a
high isolation capability and a low thermal resistance between the tab and
TO-220 FULLPAK
external heatsink. This isolation is equivalent to using a 100 micron mica barrier
with standard TO-220 product. The Fullpak is mounted to a heatsink using a
single clip or by a single screw fixing.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 14
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 9.8 A
I
DM
PD @TC = 25°C Power Dissipation 45 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
T
J
T
STG
Pulsed Drain Current 56
Linear Derating Factor 0.30 W/°C
Gate-to-Source Voltage ±16 V
Single Pulse Avalanche Energy 340 mJ
Avalanche Current 8.4 A
Repetitive Avalanche Energy 4.5 mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 3.3
Junction-to-Ambient ––– 65
°C/W
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IRLI3615
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage 150 ––– ––– VVGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.18 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance
––– ––– 0.085 VGS = 10V, ID = 8.4A
––– ––– 0.095 Ω V
= 5.0V, ID = 8.4A
GS
Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
Forward Transconductance 14 ––– ––– SVDS = 50V, ID = 8.4A
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage ––– ––– 100
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
––– ––– 25
––– ––– 250 VDS = 120V, VGS = 0V, TJ = 150°C
µA
nA
= 150V, VGS = 0V
V
DS
= 16V
V
GS
Total Gate Charge ––– ––– 140 ID = 8.4A
Gate-to-Source Charge ––– ––– 9.5 nC VDS = 120V
Gate-to-Drain ("Miller") Charge ––– ––– 53 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 8.3 ––– VDD = 75V
Rise Time ––– 20 –––
Turn-Off Delay Time ––– 110 ––– RG = 6.2Ω, VGS = 10V
ns
ID = 8.4A
Fall Time ––– 53 ––– RD = 8.9Ω, See Fig. 10
Internal Drain Inductance ––– 4.5 –––
Internal Source Inductance ––– 7.5 –––
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
Input Capacitance ––– 1600 ––– VGS = 0V
Output Capacitance ––– 290 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 150 ––– ƒ = 1.0MHz, See Fig. 5
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
14
56
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 8.4A, VGS = 0V
Reverse Recovery Time ––– 180 270 ns TJ = 25°C, IF = 8.4A
Reverse RecoveryCharge ––– 1130 1700 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 9.5mH
J
= 8.4A. (See Figure 12)
AS
≤ 8.4A, di/dt ≤ 510A/µs, V
DD
≤ V
(BR)DSS
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Caculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the
package refer to Design Tip # 93-4.
,
TJ ≤ 175°C.
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D
S
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IRLI3615
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
100
VGS
TOP
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM
2.7V
2.7V
20µs PULSE WIDTH
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
T = 25 C
J
°
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
VGS
TOP
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM
2.7V
20µs PULSE WIDTH
T = 175 C
J
V , Drain-to-Source Voltage (V)
DS
2.7V
°
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.5
3.0
I =
D
14A
°
T = 175 C
J
10
D
I , Drain-to-Source Current (A)
V = 50V
DS
1
2.0 3.0 4.0 5.0 6.0 7.0
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
10V
GS
°
Vs. Temperature
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IRLI3615
100000
10000
1000
C, Capacitance(pF)
100
10
1 10 100 1000
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
Ciss
Coss
Crss
+ Cgd, C
gs
gd
+ C
ds
gd
iss
C
rss
C
oss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
SHORTED
ds
20
I =
8.4A
D
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
0
0 20 40 60 80 100 120 140
Q , Total Gate Charge (nC)
G
V = 120V
DS
V = 75V
DS
V = 30V
DS
FOR TEST CIRCUIT
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
13
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10
T = 175 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4
°
J
°
T = 25 C
J
V ,Source-to-Drain Voltage (V)
SD
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
100
10
1
, Drain-to-Source Current (A)
I
Tc = 25°C
D
Tj = 175°C
Single Pulse
0.1
1 10 100 1000
V
, Drain-toSource Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
100µs
1ms
1
0ms
Forward Voltage
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IRLI3615
R
D.U.T.
D
+
V
DD
-
14
12
10
V
DS
V
GS
R
G
8
6
D
4
I , Drain Current (A)
2
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
thJC
1
0.20
0.10
0.05
0.02
0.1
0.01
Thermal Response (Z )
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
P
DM
t
1 2
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLI3615
A
15V
DRIVER
+
-
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
V
DD
1000
TOP
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
D
3.4A
5.9A
8.4A
°
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
+
V
-
D
Fig 13b. Gate Charge Test Circuit
DS
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IRLI3615
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
P.W.
Period
+
-
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFETS
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IRLI3615
PART NUMBER
LOGO
RECTIFIER
INTERNATIONAL
ASS E MB L Y
LOT CODE
WEE K 24
LINE K
YEAR 9 = 1999
DATE CO DEIN THE ASSEMBLY LINE "K"
A SSEMBLED ON WW 24 1999
LOT CODE 3432
IRFI840G
34 32
924K
EXAMPL E: T HI S IS AN IR F I840G
WI TH ASSEMBL Y
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
16.00 (.630)
15.80 (.622)
13.70 (.540)
13.50 (.530)
1.40 (.055)
3X
1.05 (.042)
2.54 (.100)
2X
10.60 (.417)
10.40 (.409)
1 2 3
3X
ø
3.70 (.145)
3.20 (.126)
1.15 (.045)
MIN .
3.30 (.130)
3.10 (.122)
0.90 (.035)
0.70 (.028)
0.25 (.010)
3.40 (.133)
3.10 (.123)
- A -
- B -
M
A M B
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
2.80 (.110)
2.60 (.102)
NOTES:
1 DIMENSIONING & TOLERANCING
P ER ANS I Y14.5M, 1982
2 CONTROLLING DIMENSION: INCH.
0.48 (.019)
3X
0.44 (.017)
2.85 (.112)
2.65 (.104)
LEAD ASSIGNMENTS
1 - G A T E
2 - D R AIN
3 - S O U RC E
MINIMUM CREEPAGE
DISTANCE BETW EEN
A-B-C-D = 4.80 (.189)
C
D
A
B
Part Marking Information
TO-220 Fullpak
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
8 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/02
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