Datasheet IRL7833SPBF Datasheet

Applications

Absolute Maximum Ratings

V

Conti n uous Drai n Cur r e nt, V

@ 10V

Pulsed Drain Current

Maximum Power Dissipation

Thermal Resistance

Case-to-Sin k , Fl at, Greas ed Surfac e

Junction-t o- Ambien t (P CB Mount)

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification for Telecom and Consumer Use

l Lead-Free

Benefits

V

DSS

30V

PD - 95270

IRL7833PbF

IRL7833SPbF

IRL7833LPbF

HEXFET® Power MOSFET

R

DS(on)

3.8m

max

:

Qg

32nC

l Very Low RDS(on) at 4.5V V l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage

GS

and Current

Parameter Units

DS

V

GS

@ TC = 25°C

I

D

ID @ TC = 100°C I

DM

PD @TC = 25°C

@TC = 100°C

P

D

T

J

T

STG

R

JC

θ

R

CS

θ

R

JA

θ

R

JA

θ

Drain-to-Sour ce Voltage V Gate-to-Source Volt age

GS

Conti n uous Drai n Cur r e nt, V

c

Linear D er ating Factor W/°C Operating Junction and °C

Stor ag e Temperat ur e Ra ng e Mount ing Torque, 6-32 or M 3 s c r ew

@ 10V

GS

g g

Parameter Typ. Max. Units

Junction-to-Case ––– 1.04

Junction-to-Ambient

h

g

TO-220AB

IRL7833

D2Pak

IRL7833S

TO-262

IRL7833L

Max.

30

± 20

f

150

f

110

600 140

72

0.96

-55 to + 175

y

in (1.1Nym)

10 lbf

h

0.50 ––– °C/W ––– 62 ––– 40

A

W

Notes  through  are on page 12

www.irf.com 1

05/18/04

IRL7833/S/LPbF

S

D

G

BV

V

/∆T

R

m

V

/∆T

I

Q

QswSwitch Charge (Q

+ Qgd)

Q

t

C

Avalanche Characteristics

EASSingle Pul se Av a la nc h e Energ y

IARAvalanche Current

EARRepeti ti ve Avalanche Energy

Diode Characterist ics

I

V

t

Q

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

DSS

∆Β

DSS

DS(on)

GS(th)

∆

GS(th)

DSS

GSS

gfs Forward Tra nsconductance 150 ––– ––– S

g

gs1 gs2 gd godr

oss d(on) r d(off) f

iss

oss

rss

Drain-to-Sou r c e Br eakdown V ol t a ge 30 ––– ––– V Breakdown Voltag e Temp. Coefficient ––– 18 ––– mV/°C

J

Stat ic D r ai n- to-Sou rce On-Res i s tance ––– 3.1 3.8

––– 3.7 4.5 Gate Threshold Voltage 1.4 ––– 2.3 V Gate Th res hold Voltage Coe fficien t ––– -11 – –– mV/°C

J

Drain-to-Sou r c e Le akage Cur rent ––– ––– 1.0 µA

––– ––– 150 Gate-to-Sour c e Forward Lea k age ––– ––– 100 nA Gate-to-Sou rce Rever s e Le akage ––– ––– -100

Total Gate Charge ––– 32 47 Pre-Vth Gate-to-Source Charge ––– 8.7 ––– Post-Vth Gate-to-Source Charge ––– 5.1 ––– nC Gate-to-Drain Charge ––– 13 ––– Gate Cha r ge Ov e r dr i v e ––– 5.3 ––– See Fig. 16

gs2

––– 18 ––– Output Charge ––– 22 ––– nC Turn-On Delay Time ––– 18 ––– Rise Time ––– 50 ––– ns Turn-Off Delay Time ––– 21 ––– Fall Tim e ––– 6.9 –– – Input Capacitance ––– 4170 ––– Output Capacitance ––– 950 ––– pF Reverse Transfer Capacitance ––– 470 –––

Conditions

VGS = 0V, ID = 250µA Referen c e to 25°C, I

Ω

V

= 10V, ID = 38A

GS

V

= 4.5V, ID = 30A

GS

VDS = VGS, ID = 250µA

V

= 24V, VGS = 0V

DS

= 24V, VGS = 0V, TJ = 125°C

V

DS

V

= 20V

GS

= -20V

V

GS

= 15V, ID = 30A

V

DS

V

= 16V

DS

V

= 4.5V

GS

I

= 30A

D

= 16V, VGS = 0V

V

DS

= 15V, VGS = 4.5V

V

DD

ID = 26A Clampe d I n ductiv e Load

= 0V

V

GS

= 15V

V

DS

ƒ = 1.0MHz

= 1mA

D

f

S

SM

SD

rr

2 www.irf.com

Parameter Units

dh

c

c

Typ.

––– ––– –––

Paramet e r Min. Typ . Max. Units

Contin uous Source Current ––– ––– (Body Diode) A

Pulsed Source Current ––– ––– 600 (Body Diode)

ch

Diode Forward Voltage ––– ––– 1.2 V Reverse Recovery Time ––– 42 63 ns Reverse Recovery Charge ––– 34 51 nC

150

f

Max.

560

30 14

mJ

A

mJ

Conditions

MOSFET symbol showing the

integral reverse p-n junct ion diode.

TJ = 25°C, IS = 30A, VGS = 0V

= 25°C, IF = 30A, VDD = 15V

T

J

di/dt = 100A/µs

f

IRL7833/S/LPbF

1000

) A

(

t

n

e

r

100

r

u C e

c

r

u

o S

-

o

t

-

n

10

i

a

r D

,

D

I

2.7V

20µs PULSE WIDTH Tj = 25°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

1000

)

Α

(

t

n

e

r

u C e

c

r

100

u

o S

-

o

t

-

n

i

a

r D

,

D

I

TJ = 25°C

TJ = 175°C

V

= 15V

DS

20µs PULSE WIDTH

10

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-t o-Source Vol tage (V)

TOP 10V

BOTTOM 2.7V

VGS

7.0V

4.5V

3.7V

3.5V

3.3V

3.0V

1000

) A

(

t

n

e

r

100

r

u C e

c

r

u

o S

-

o

t

-

n

10

i

a

r D

,

D

I

2.7V

20µs PULSE WIDTH Tj = 175°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

2.0

e

c

n

a

t

s

i

s

e R n O e

c

r

u

o S

-

o

t

-

n

i

a

r D

,

)

n

o

( S D

R

ID = 75A V

= 10V

GS

1.5

)

d

e

z

i

l

a m

r

o N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

TOP 10V

BOTTOM 2.7V

VGS

7.0V

4.5V

3.7V

3.5V

3.3V

3.0V

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

Vs. Temperature

www.irf.com 3

IRL7833/S/LPbF

100000

) F

10000

p

(

e

c

n

a

t

i

c

a

p

a C

,

1000

C

100

V

= 0V, f = 1 MHZ

GS

C

= C

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

C

iss

C

oss

C

rss

1 10 100

VDS, Drain-to-Source Voltage (V)

SHORTED

ds

gd

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.00

) A

(

100.00

t

n

e

r

u C n

i

a

r

10.00

D e

s

r

e

v

e R

,

1.00

D S

I

0.10

0.0 0.5 1.0 1.5 2.0 2.5 3.0

TJ = 25°C

VSD, Source-to-Drain Voltage (V)

TJ = 175°C

V

GS

= 0V

12.0 ID= 30A

)

10.0

V

( e

g

a

t

l

8.0

o V

e

c

r

u

6.0

o S

-

o

t

-

e

t

4.0

a G

,

S G

2.0

V

0.0 0 5 10 15 20 25 30 35 40

VDS= 24V VDS= 15V

Q

Total G ate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

) A

(

t

100

n

e

r

u C e

c

r

10

u

o S

-

o

t

-

n

i

a

r

1

D ,

Tc = 25°C

D

I

Tj = 175°C Single Pulse

0.1 1 10 100

OPERATION IN THIS AREA LIMITED BY RDS(on)

100µsec

1msec

10msec

VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

IRL7833/S/LPbF

160

LIMITED BY PACKAGE

120

80

D

I , Drain Current (A)

40

0

25 50 75 100 125 150 175

TC, Case Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

10

2.5

) V

(

2.0

e

g

a

t

l

o V

d

l

1.5

o

h

s

e

r

h

t

1.0

e

t

a G

)

h

t

(

0.5

S G

V

0.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

Fig 10. Threshold Voltage Vs. Temperature

thJC

1

D = 0.50

0.20 P

1 2

DM

t

1

t

2

0.10

0.1

0.05

Thermal Response (Z )

0.02

0.01

0.00001 0.0001 0.001 0.01 0.1 1

SINGLE PULSE

(THERMAL RESPONSE)

t , Rectangular Pulse Duration (sec)

1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

J DM thJC C

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRL7833/S/LPbF

S

Current Regulator

I

A

9

+

-

15V

V

DS

R

G

20V

V

GS

L

D.U.T

I

AS

Ω

0.01

t

p

DRIVER

+

V

DD

-

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

AS

Fig 12b. Unclamped Inductive Waveforms

2000

TOP

1600

1200

800

400

AS

E , Single Pulse Avalanche Energy (m J )

0

25 50 75 100 125 150 175

BOTTOM

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

L

V

DS

D

I

D

12A 21A 30A

V

DD

D.U.T

V

Same Type as D.U.T.

GS

Pulse W i dt h < 1µs

Duty Factor < 0.1%

12V

.2µF

50KΩ

.3µF

D.U.T.

+

Fig 14a. Switching Time Test Circuit

V

D

-

V

DS

0%

V

GS

3mA

10%

I

G

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

I

D

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 14b. Switching Time Waveforms

6 www.irf.com

IRL7833/S/LPbF

R V

+

-

Id





Reverse Recovery Current

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

e-Applied oltage

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P.W.

Period

VGS=10V

V

DD

I

SD

*

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Vds

Vgs

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

www.irf.com 7

IRL7833/S/LPbF

f

P P

f

)

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

= I

()

rms

⎛ ⎜

+ I ×

⎝

+ Qg× Vg× f

()

Q

⎛

+

⎝

This simplified loss equation includes the terms Q and Q

charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.

the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I gins to change. Minimizing Q reducing switching losses in Q1.

put capacitance of the MOSFET during every switching cycle. Figure A shows how Q parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.

which are new to Power MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

8 www.irf.com

+ P

2

× R

ds(on )

Q

gd

× Vin× f

i

g

oss

×Vin× f

2

at which time the drain voltage be-

dmax

switching

⎞ ⎟

⎠

⎞ ⎠

and Q

gs1

+ P

+ I ×

+ P

drive

⎛

Q

gs2

⎜

i

⎝

g

, can be seen from

gs2

is a critical factor in

gs2

is formed by the

oss

of the

ds(on)

output

× Vin×

Synchronous FET

The power loss equation for Q2 is approximated

by;

= P

loss

conduction

= I

loss

+ Qg× Vg× f

+

rms

()

⎛

Q

⎜ ⎝

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R

portant characteristic; however, once again the im-

⎞ ⎟

portance of gate charge must not be overlooked since

⎠

it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly , the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

gs2

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and of f there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.

Figure A: Q

+ P

2

× R

ds(on)()

oss

×Vin× f

2

must be minimized to reduce the

gs1

Characteristic

oss

drive

+ P

⎞ ⎠

*

output

+ Q

(

× Vin×

rr

ds(on)

oss

is an im-

and re-

N

.

TO-220AB Package Outline

R

Dimensions are shown in millimeters (inches)

IRL7833/S/LPbF

10.54 (.415)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.09 (.555)

13.47 (.530)

1.40 (.055)

3X

1.15 (.045)

2.54 (.100)

OTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INC LUD E BURR S

2X

10.29 (.405)

4

1 2 3

3X

0.36 (.014) M B A M

6.47 (.255)

6.10 (.240)

1.15 (.045) MIN

4.06 (.160)

3.55 (.140)

0.93 (.037)

0.69 (.027)

3.78 (.149)

3.54 (.139)

- A -

4.69 (.185)

4.20 (.165)

- B -

1.32 (.052)

1.22 (.048)

2.92 (.115)

2.64 (.104)

LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

0.55 (.022)

3X

0.46 (.018)

TO-220AB Part Marking Information

EXAMPLE:

www.irf.com 9

THIS IS AN IRF1010 LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN THE AS SEMBLY LINE "C"

Note: "P" in asse mbly line position indicates "Lead-Free"

INTERNAT IONAL

RE CTIF IE R

LOGO

AS SEMBLY LOT CODE

PART NUMBE

DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C

IRL7833/S/LPbF

R

2

Pak Package Outline

D

D2Pak Part Marking Information

THIS IS AN IRF530S WITH LOT CODE 8024

ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L"

Note: "P" in assembly line pos i ti on indi cates "L ead- F r ee"

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LO T CODE

F530S

PA RT NUM BE

DATE CODE YEAR 0 = 2000 WEEK 02 LINE L

OR

INTERNATIONA L

RECTIFIER

LOGO

ASSEMBLY LOT CODE

F530S

10 www.irf.com

PART NUMBER

DATE CODE P = DESIGNA TES LEAD-FREE

PRODUCT (OPTIONAL)

YEAR 0 = 2000 WE E K 02

A = ASSEMBLY SITE CODE

TO-262 Package Outline

IRL7833/S/LPbF

TO-262 Part Marking Information

EXAMPLE:

THIS IS AN IRL3103L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE " C"

Note: "P" in ass embly line

pos ition indi cates "L ead-Free"

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CO DE

PAR T NUMBER

DATE CODE YEAR 7 = 1997 WEEK 19 LIN E C

OR

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CO DE

www.irf.com 11

PAR T NUMBER

DATE CODE P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

YEAR 7 = 1997 WEEK 19

A = AS S E MB L Y S I T E CODE

IRL7833/S/LPbF

TRR

F

) )

)

D2Pak Tape & Reel Information

Dimensions are shown in millimeters (inches)

EED DIRECTION

TRL

EED DIRECTION

1.85 (.073)

1.65 (.065)

10.90 (.429)

10.70 (.421)

4.10 (.161)

3.90 (.153)

1.60 (.063)

1.50 (.059)

11.60 (.457)

11.40 (.449)

16.10 ( .634)

15.90 ( .626)

1.60 (.063)

1.50 (.059)

1.75 (.069)

1.25 (.049)

15.42 (.609)

15.22 (.601)

0.368 (.0145)

0.342 (.0135)

24.30 (.957

23.90 (.941

4.72 (.136)

4.52 (.178)

13.50 (.532)

12.80 (.504)

330.00 (14.173) MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

27.40 (1.079)

23.90 (.941)

4

26.40 (1.039)

24.40 (.961)

3

60.00 (2.362 MIN.

30.40 (1.197) MAX.

4

Notes:

 Repetitive rating; pulse width limited by max. junction temperature.  Starting T

= 25°C, L = 1.3mH, RG = 25Ω, I

J

AS

= 30A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.  Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to

application note #AN-994.

 This is only applied to TO-220AB package.

TO-220AB package isnot recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.05/04

12 www.irf.com

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/