l Logic-Level Gate Drive
l Advanced Process Technology
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
Description
G
D
V
= 100V
DSS
R
DS(on)
= 0.18Ω
ID = 10A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 watts. The low thermal
resistance and low package cost of the TO-220
TO-220AB
contribute to its wide acceptance throughout the
industry.
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V10
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V7.1A
I
DM
PD @TC = 25°CPower Dissipation48W
V
GS
E
AS
I
AR
E
AR
dv/dtPeak Diode Recovery dv/dt 5.0V/ns
T
J
T
STG
Pulsed Drain Current 35
Linear Derating Factor0.32W/°C
Gate-to-Source Voltage ± 16V
Single Pulse Avalanche Energy85mJ
Avalanche Current6.0A
Repetitive Avalanche Energy4.8m J
Operating Junction and-55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew10 lbf•in (1.1N•m)
Fall Time–––22–––RD = 8.2Ω, See Fig. 10
Internal Drain Inductance––– 4.5 –––
Internal Source Inductance––– 7.5–––
Between lead,
nH
6mm (0.25in.)
from package
and center of die contact
Input Capacitance–––440 –––VGS = 0V
Output Capacitance–––97–––pFVDS = 25V
Reverse Transfer Capacitance–– –50–––ƒ = 1.0MHz, See Fig. 5
Diode Forward Voltage––– –– –1 .3VTJ = 25°C, IS = 6.0A, VGS = 0V
Reverse Recovery Time––– 110 160n sTJ = 25°C, IF =6.0A
Reverse RecoveryCharge––– 41 0 620nCdi/dt = 100A/µs
Forward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
SD
TJ ≤ 175°C
= 25°C, L = 4.7mH
J
= 6.0A. (See Figure 12)
AS
Pulse width ≤ 300µs; duty cycle ≤ 2%.
10
A
35
≤ 6.0A, di/dt ≤ 340A/µs, V
showing the
p-n junction diode.
DD
≤ V
(BR)DSS
,
D
G
S
Page 3
IRL520N
)
A
)
A
A
A
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
1
2.5V
D
I , D rain -to -S o u rc e Curren t ( A )
20µs PULSE WIDTH
T = 25°C
0.1
0.1110100
V , Drain- to -S o u r ce Voltage (V
DS
J
Fig 1. Typical Output Characteristics
100
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
2.5V
1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
T = 175°C
0.1
0.1110100
V , Drain- to -S o u r ce Voltage (V
DS
J
Fig 2. Typical Output Characteristics
3.0
I = 10 A
D
T = 25°C
J
T = 175°C
10
1
D
I , D rain -to-S o urc e Curren t (A )
0.1
246810
V , G ate -to-S ou rce V oltag e (V)
GS
J
V = 50V
DS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Norm alized)
1.0
0.5
DS(on)
R , D r ain -to- S ou r c e On R es i sta n c e
0.0
-60 -40 -20020 40 60 80 100 120 140 160 180
T , Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V = 10 V
GS
Page 4
IRL520N
)
A
)
A
A
)
A
g
800
600
400
V = 0V, f = 1M Hz
GS
C = C + C , C S H O RTE D
iss gs gd ds
C = C
rss gd
C = C + C
oss ds g d
C
iss
C
oss
C, Capacitance (pF)
200
C
rss
0
110100
V , Drain- to -S o u rc e Voltage (V
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
T = 175°C
10
J
T = 25 °C
J
15
I = 6.0 A
V , G a te -to -S o u rc e Vol tag e (V )
12
GS
D
9
6
3
V = 8 0 V
DS
V = 5 0 V
DS
V = 2 0 V
DS
FOR TEST CIRCUIT
0
0510152025
Q , To ta l Gate Cha rge (nC
G
SE E F IG U RE 1 3
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
OP ERA T IO N IN T H IS A R E A L IMITE D
BY R
10
DS(on)
10µs
100µs
1ms
1
SD
I , R ev er se D r a in Curre nt (A)
0.1
0.40.60.81.01.21.4
V , Source-to-Drain Voltage (V)
SD
V = 0V
Fig 7. Typical Source-Drain Diode
GS
1
D
I , Drain Current (A)
T = 25 °C
C
T = 17 5 °C
J
Sin
0.1
le Pu l s e
1101001000
V , Drain- to -S o u r ce Voltage (V
DS
10ms
Fig 8. Maximum Safe Operating Area
Forward Voltage
Page 5
IRL520N
A
10
8
6
4
D
I , D ra in C u rre n t (A mp s)
2
0
255075100125150175
T , Case Temperature (°C)
C
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
R
V
DS
V
GS
R
G
D
D.U.T.
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
+
V
DD
-
D = 0.50
thJC
1
0.20
0.10
0.05
P
1 2
DM
t
1
t
2
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty factor D = t / t
2. Peak T =Px Z+ T
0.01
0.000010.00010.0010.010.1
t , Rectangular Pulse Duration (sec)
1
JDMthJCC
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRL520N
A
)
A
15V
DRIVER
+
-
V
DD
R
V
G
10V
DS
L
D.U.T
I
AS
Ω
t
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
200
I
TO P 2.4 A
4.2A
160
120
80
40
AS
E , S ing le Puls e A v a lan c he Energ y (mJ)
0
255075100125150175
Starting T , Junction Temperature (°C
J
BOTTOM 6.0A
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
D
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
5.0 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
.3µF
D.U.T .
3mA
I
G
Current Sampling Resistors
I
+
D
Fig 13b. Gate Charge Test Circuit
V
DS
-
Page 7
IRL520N
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
P.W.
Period
+
-
VGS=10V
V
DD
*
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. ISDWaveform
Body Diode Forward
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFETS
Current
di/dt
Diode Recovery
dv/dt
V
DD
I
SD
Page 8
IRL520N
A
A
Package Outline
TO-220AB Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
1.40 (.055)
3X
1.15 (.045)
2.54 (.100)
NOTES:
1 DIM EN SIO NIN G & TO L ER AN CI N G PE R A NS I Y1 4 . 5 M , 19 82. 3 OU TL IN E C ON FO RM S T O JE D EC O U T LIN E TO -22 0 AB .
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
10.29 (.405)
1 2 3
2X
Part Marking Information
TO-220AB
EXAMPLE: THISISANIRF1010
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
W ITH A SS EM BL Y
LOT CODE 9B1M
LO T CO DE 9 B1 M
3.78 (.149)
3.54 (.139)
6.47 (.255)
6.10 (.240)
4
1.15 (.045)
M IN
4.06 (.160)
3.55 (.140)
0.93 (.037)
3X
0.69 (.027)
0.36 (.01 4) M B A M
INTERNATIONAL
INTERN A TION A L
RECTIFIER
RE CTIFIER
LOGO
L OG O
ASSEMBLY
ASSEMBLY
LOTCODE
LO T C OD E
- A -
4.69 (.185)
4.20 (.165)
IRF1010
I RF1010
9246
9246
9B 1M
9B 1 M
- B -
1.32 (.052)
1.22 (.048)
2.92 (.115)
2.64 (.104)
3X
LEAD ASSIGNMENTS
1 - GAT E
2 - DRA IN
3 - SOU RC E
4 - DRA IN
0.55 (.022)
0.46 (.018)
PARTNUMBER
PART NUMB ER
DATECODE
DATE CODE
(YYWW)
(YYWW)
YY = YEAR
YY = YEAR
WW = WEEK
WW = WEEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/Data and specifications subject to change without notice.5/98
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