Page 1
PD - 9.1693
PRELIMINARY
l Advanced Process Technology
l Surface Mount
l Optimized for 4.5V-7.0V Gate Drive
l Ideal for CPU Core DC-DC Converters
l Fast Switching
Description
These HEXFET Power MOSFETs were designed
specifically to meet the demands of CPU core DC-DC
converters. Advanced processing techniques
combined with an optimized gate oxide design results
in a die sized specifically to offer maximum efficiency
at minimum cost.
2
The D
Pak is a surface mount power package capable
of accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
2
D
Pak is suitable for high current applications because
of its low internal connection resistance and can
dissipate up to 2.0W in a typical surface mount
application.
IRL3402S
HEXFET® Power MOSFET
D
V
= 20V
DSS
G
R
S
2
D Pak
DS(on)
= 85A
I
D
= 0.01Ω
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 4.5V 85
@ TC = 100°C Continuous Drain Current, VGS @ 4.5V 54 A
I
D
I
DM
PD @TC = 25°C Power Dissipation 110 W
V
GS
V
GSM
E
AS
I
AR
E
AR
dv/d t Peak Diode Recovery dv/dt 5.0 V/ns
T
J
T
STG
Pulsed Drain Current 340
Linear Derating Factor 0.91 W/°C
Gate-to-Source Voltage ± 10 V
Gate-to-Source Voltage 14 V
(Start Up Transient, tp = 100µs)
Single Pulse Avalanche Energy 290 mJ
Avalanche Current 51 A
Repetitive Avalanche Energy 11 mJ
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
Junction-to-Case ––– 1.1
Junction-to-Ambient ( PCB Mounted,steady-state)** –– – 40 °C/W
°C
10/31/97
Page 2
IRL3402S
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage 20 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient –– – 0.02 – –– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance
––– ––– 0.010 VGS = 4.5V, ID = 51A
––– ––– 0.008
Ω
VGS = 7.0V, ID = 51A
Gate Threshold Voltage 0.70 ––– ––– V VDS = VGS, ID = 250µA
Forward Transconductance 65 ––– ––– S VDS = 10V, ID = 51A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 16V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -10V
µA
nA
= 20V, VGS = 0V
V
DS
= 10V
V
GS
Total Gate Charge ––– ––– 78 ID = 51A
Gate-to-Source Charge ––– ––– 18 nC VDS = 10V
Gate-to-Drain ("Miller") Charge ––– ––– 30 VGS = 4.5V, See Fig. 6
Turn-On Delay Time ––– 10 ––– VDD = 10V
Rise Time ––– 140 –––
Turn-Off Delay Time ––– 80 ––– RG = 5.0Ω, VGS = 4.5V
ns
ID = 51A
Fall Time ––– 120 ––– RD = 0.19Ω,
Between lead,
Internal Source Inductance ––– 7.5 – – –
nH
and center of die contact
Input Capacitance ––– 3300 ––– VGS = 0V
Output Capacitance ––– 1400 ––– pF VDS = 15V
Reverse Transfer Capacitance ––– 510 ––– ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting T
RG = 25Ω, I
I
SD
TJ ≤ 150°C
** When mounted on FR-4 board using minimum recommended footprint.
For recommended footprint and soldering techniques refer to application note #AN-994.
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
85
340
showing the
A
p-n junction diode.
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 51A, VGS = 0V
Reverse Recovery Time ––– 72 1 10 ns TJ = 25°C, IF = 51A
Reverse RecoveryCharge ––– 160 240 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
= 25°C, L = 0.55 mH
J
=51A.
AS
≤ 51A, di/dt ≤ 82A/µs, V
DD
≤ V
(BR)DSS
Uses IRL3402 data and test conditions
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the
,
package refer to Design Tip # 93-4
D
G
S
Page 3
IRL3402S
1000
100
D
I , Drain-to-Source Current (A)
TOP
BOTTOM
VGS
7.00V
5.00V
4.50V
3.50V
3.00V
2.70V
2.50V
2.25V
2.25V
20µs PULSE WIDTH
°
T = 25 C
10
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
1000
J
1000
100
TOP
BOTTOM
VGS
7.00V
5.00V
4.50V
3.50V
3.00V
2.70V
2.50V
2.25V
2.25V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
10
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
T = 150 C
°
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
2.0
I =
D
85A
°
T = 25 C
J
°
100
D
I , Drain-to-Source Current (A)
10
2 3 4 5 6
V , Gate-to-Source Voltage (V)
GS
T = 150 C
J
1
V = 50V
DS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
1.5
1.0
(Normalized)
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
4.5V
10V
Page 4
IRL3402S
6000
5000
4000
3000
2000
C, Capacitance (pF)
1000
0
1 10 100
V
=
0V,
GS
C
=
iss gs gd , ds
C
=
rss gd
C
=
oss ds gd
V , Drain-to-Source Voltage (V)
DS
f = 1MHz
C
+ C
C SHORTED
C
C
+ C
C
iss
C
oss
C
rss
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
°
T = 150 C
J
100
T = 25 C
J
°
15
I =
85 A
D
V = 16V
DS
10
5
GS
V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 20 40 60 80 100 120
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10000
OPERATION IN THIS AREA LIMITED
1000
BY R
DS(on)
10us
13
10
1
SD
I , Reverse Drain Current (A)
V = 0 V
0.1
0.2 0.6 1.0 1.4 1.8 2.2
V ,Source-to-Drain Voltage (V)
SD
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
D
I , Drain Current (A)I , Drain Current (A)
10
°
= 25 C
C
T T= 150 C
Single Pulse
1
1 10 100
°
J
V , Drain-to-Source Voltage (V)
DS
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
Page 5
IRL3402S
100
LIMITED BY PACKAGE
80
60
40
D
I , Drain Current (A)
20
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
600
TOP
500
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 10. Maximum Avalanche Energy
Vs. Drain Current
I
D
23A
32A
51A
°
thJC
1
D = 0.50
0.20
P
1 2
DM
t
1
t
2
0.10
0.1
0.05
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRL3402S
0.020
( Ω )
0.015
0.010
DS (on)
0.005
R , Drain-to-Source On Resistance
0 50 100 150 200 250 300 350
VGS = 4.5V
I , Drain Current (A)
D
VGS = 7.0V
0.012
( Ω )
0.011
0.010
0.009
0.008
0.007
DS (on)
0.006
R , Drain-to-Source On Resistance
2 3 4 5 6 7 8
V , Gate-to-Source Voltage (V)
GS
ID = 85A
Fig 12. On-Resistance Vs. Drain Current Fig 13. On-Resistance Vs. Gate Voltage
Page 7
D2Pak Package Outline
IRL3402S
10.54 (.415)
1.40 (.055)
MAX.
1.78 (.070)
1.27 (.050)
1.40 (.055)
3X
1.14 (.045)
5.08 (.200)
NOTES:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONI NG & TOLERANCING PER ANSI Y14.5M, 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
10.29 (.405)
- A 2
1 3
15.49 (.610)
14.73 (.580)
0.93 (.037)
3X
0.69 (.027)
0.25 (.010) M B A M
Part Marking Information
D2Pak
4.69 (.185)
4.20 (.165)
5.28 (.208)
4.78 (.188)
0.55 (.022)
0.46 (.018)
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
10.16 (.400)
RE F.
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF.
MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2X
2.54 (.100)
2X
INTERNATIONAL
REC TIFIER
L OGO
ASSEMBLY
LOT CODE
F530S
9246
9B 1M
PART NUMBER
A
DATE CODE
(YYW W)
YY = YEAR
WW = WEEK
Page 8
IRL3402S
Tape & Reel Information
D2Pak
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
1.65 (.065)
TRL
10.90 (.429)
10.70 (.421)
FEED DIRECTION
13.5 0 (. 532 )
12.8 0 (. 504 )
330.0 0
(14.17 3)
M AX .
NOT ES :
1. CO MFO R M S TO EIA -418 .
2. CONTRO LLING DIMEN SION: MILLIMETER .
3. DIME NS IO N MEASURE D @ HUB .
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
11.6 0 (.457 )
11.4 0 (.449 )
1.75 (.0 69 )
1.25 (.0 49 )
16.10 (.634)
15.90 (.626)
15.4 2 (.609 )
15.2 2 (.601 )
27.4 0 (1 .079)
23.9 0 (.9 41)
4
26.40 (1. 03 9)
24.40 (.961)
3
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
60.0 0 (2 .362)
M IN.
30.4 0 (1 .197)
M A X .
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/ Data and specifications subject to change without notice. 10/97
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