Datasheet irgpc60lc Datasheet

HEXFET® Power MOSFET

Ultra Low Gate Charge
Reduced Gate Drive Requirement
Enhanced 30V Vgs Rating
Reduced C
Isolated Central Mounting Hole
Dynamic dv/dt Rated
Repetitive Avalanche Rated

Description

This new series of Low Charge HEXFET Power MOSFETs achieve significantly
lower gate charge over conventional MOSFETs. Utilizing advanced Hexfet
technology the device improvements allow for reduced gate drive requirements,
faster switching speeds and increased total system savings. These device
improvements combined with the proven ruggedness and reliability of HEXFETs
offer the designer a new standard in power transistors for switching applications.

The TO-247 package is preferred for commercial-industrial applications where
higher power levels preclude the use of TO-220 devices. The TO-247 is similar
but superior to the earlier TO-218 package because of its isolated mounting hole.

iss

, C

oss

, C

rss

PD - 9.1234

IRFPC60LC

V

= 600V

DSS

R
ID = 16A

DS(on)

= 0.40 Ω

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 16
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 10 A
I

DM

PD @TC = 25°C Power Dissipation 280 W

V

GS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt 3.0 V/ns
T

J

T

STG

Pulsed Drain Current 64

Linear Derating Factor 2.2 W/°C
Gate-to-Source Voltage ±30 V
Single Pulse Avalanche Energy 1000 mJ
Avalanche Current 16 A
Repetitive Avalanche Energy 28 mJ

Operating Junction and -55 to + 150
Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case)
Mounting torque, 6-32 or M3 screw. 10 lbf•in (1.1N•m)

Thermal Resistance

Parameter Min. Typ. Max. Units

R

θJC

R

θCS

R

θJA

Junction-to-Case –––– –––– 0.45
Case-to-Sink, Flat, Greased Surface –––– 0.24 –––– °C/W
Junction-to-Ambient –––– –––– 40

Revision 0

IRFPC60LC

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

∆V

(BR)DSS

R

DS(ON)

V

GS(th)

g

fs

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 600 ––– ––– V VGS = 0V, ID = 250µA

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.63 ––– V/°C Reference to 25°C, ID = 1mA

J

Static Drain-to-Source On-Resistance ––– ––– 0.40 Ω VGS = 10V, ID = 9.6A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Forward Transconductance 11 ––– ––– S VDS = 50V, ID = 9.6A

Drain-to-Source Leakage Current

Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V

––– ––– 25 VDS = 600V , VGS = 0V
––– ––– 250 VDS = 480V, VGS = 0V, TJ = 125°C

µA

nA

Total Gate Charge ––– ––– 120 ID = 16A
Gate-to-Source Charge ––– ––– 29 nC VDS = 360V
Gate-to-Drain ("Miller") Charge ––– ––– 48 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 17 ––– VDD = 300V
Rise Time ––– 57 ––– ID = 16A
Turn-Off Delay Time ––– 43 ––– RG = 4.3Ω

ns

Fall Time ––– 38 ––– RD = 18Ω, See Fig. 10

Internal Drain Inductance ––– 5.0 –––

Internal Source Inductance ––– 13 –––

Between lead,
6mm (0.25in.)

nH

from package

and center of die contact
Input Capacitance ––– 3500 ––– VGS = 0V
Output Capacitance ––– 400 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 39 ––– ƒ = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Notes:

Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

V

DD

RG = 25Ω, I

Continuous Source Current MOSFET symbol
(Body Diode) showing the
Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.

––– ––– 16

––– ––– 64

Diode Forward Voltage ––– ––– 1.8 V TJ = 25°C, IS = 16A, VGS = 0V
Reverse Recovery Time ––– 650 980 ns TJ = 25°C, IF = 16A
Reverse Recovery Charge ––– 6.0 9.0 µC di/dt = 100A/µs
Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

I

SD

TJ ≤ 150°C

= 25V, starting TJ = 25°C, L = 7.2mH

= 16A. (See Figure 12)

AS

Pulse width ≤ 300µs; duty cycle ≤ 2%.

A

≤ 16A, di/dt ≤ 140A/µs, V

DD

≤ V

(BR)DSS

,

IRFPC60LC

GS

, Gate-to-Source Voltage (V)

D

I , Drain-to-Source Current (A)

100

VGS
TOP 1 5V
10 V

8.0V

7.0V

6.0V

5.5V

5.0V

10

BOTTOM 4.5 V

1

0.1

D

I , Drain-to-Source Current (A)

4.5V

20µs PULSE WIDTH
T = 25°C

0.01

0.01 0.1 1 10 100

V , Drain-to-Source Voltage (V)

DS

C

Fig 1. Typical Output Characteristics,

TC = 25oC

100

100

VGS
TOP 1 5V
10 V

8.0V

7.0V

6.0V

5.5V

5.0V

10

BOTTOM 4.5 V

1

0.1

D

I , Drain-to-Source Current (A)

20µs PULSE WIDTH
T = 150°C

0.01

0.01 0.1 1 10 100

V , Drain-to-Source Voltage (V)

DS

C

Fig 2. Typical Output Characteristics,

TC = 150oC

3.0

I = 16A

D

4.5V

T = 15 0°C

J

10

1

0.1

0.01
4 5 6 7 8 9 10

T = 25°C

J

V = 100V

DS

20µs P U LSE WIDTH

V

2.5

2.0

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-6 0 -4 0 -20 0 20 4 0 60 8 0 100 120 140 1 6 0

T , Junction Temperature (°C)

J

V = 10V

GS

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature

IRFPC60LC

700 0

600 0

500 0

400 0

300 0

C, Capacitance (pF)

200 0

100 0

0

1 10 100

V = 0V, f = 1MHz

GS

C = C + C , C SHORTED

iss gs gd ds

C = C

rss gd

C = C + C

oss ds gd

C

iss

C

oss

C

rss

V , Drain-to-Source Voltage (V)

DS

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

100

20

I = 16A

D

16

12

8

4

GS

V , Gate-to-Source Voltage (V)

V = 360V

DS

V = 240V

DS

V = 120V

DS

FOR TEST CIRCUIT

0

0 30 60 9 0 12 0

Q , Total Gate Charge (nC)

G

SEE FIGURE 13

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1000

OPERATION IN THIS AREA LIMITED
BY R

DS(on)

10

T = 150°C

J

T = 25°C

J

SD

I , Reverse Drain Current (A)

1

0 0.4 0.8 1.2 1.6 2

V , Source-to-Drain Voltage (V)

SD

Fig 7. Typical Source-Drain Diode

Forward Voltage

V = 0V

GS

100

10µs

10

D

I , Drain Current (A)

T = 25°C

C

T = 150°C

J

Single Pulse

1

1 10 100 1000 10000

V , Drain-to-Source Voltage (V)

DS

100µs

1ms

10ms

Fig 8. Maximum Safe Operating Area

IRFPC60LC

t , Rectangu lar Pulse Duration (sec)

1

thJC

Therm al Response (Z )

R

D.U.T.

D

V

DD

V

DS

V

16

GS

R

G

12

8

D

4

I , Drain Current (Amps)

0

25 50 75 100 125 1 50

T , Case Temperature (°C)

C

Fig 9. Maximum Drain Current Vs.

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

10 V

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Case Temperature

1

D = 0.50

0.1

0.20

0.1 0

0.0 5

P

1 2

thJC

DM

t

1

t

C

2

0.02

0.01

0.001

0.01
SINGLE PUL SE

(THERM AL R E S PONSE )

0.00001 0.0001 0.001 0.01 0.1 1 10

Notes:

1. Duty fa c tor D = t / t

2. Pea k T = P x Z + T

DM

J

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

IRFPC60LC

10 V

Fig 12a. Unclamped Inductive Test Circuit

Fig 12b. Unclamped Inductive Waveforms

2400

2000

1600

1200

800

400

AS

V = 50V

E , Single Pulse Avalanche Energy (mJ)

DD

0

25 50 75 100 125 150

Starting T , Juntion Temperature (°C)

J

I
TOP 7.2A
10A
BOTTOM 16A

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

D

10 V

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

IRFPC60LC

Peak Diode Recovery dv/dt Test Circuit

D.U.T

R

G

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance
Current Transformer

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

V

DD

*

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS

IRFPC60LC

A

Package Outline

TO-247AC

Part Marking Information

TO-247AC

EXAMP LE : THIS IS AN IRFPE30
WITH ASSEMBLY
LOT CODE 3A1Q

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INTERN ATIONAL
RECTIFIER
LOGO

ASSEMBLY
LOT CODE

IRFPE30

3A1Q 9302

Data and specifications subject to change without notice.

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