Datasheet IRFZ48N Datasheet (Philips)

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N
TrenchMOS

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope using V
’trench’ technology. The device I
featuresverylowon-state resistance P
and has integral zener diodes giving T
ESD protection up to 2kV. It is R
intended for use in switched mode resistance VGS = 10 V
power supplies and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate
2 drain
3 source

TM

transistor

DS

D

tot
j

DS(ON)

Drain-source voltage 55 V
Drain current (DC) 64 A
Total power dissipation 140 W
Junction temperature 175 ˚C
Drain-source on-state 16 mΩ

tab

d

g

tab drain

123

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 20 V
Drain current (DC) Tmb = 25 ˚C - 64 A
Drain current (DC) Tmb = 100 ˚C - 45 A
Drain current (pulse peak value) Tmb = 25 ˚C - 210 A
Total power dissipation Tmb = 25 ˚C - 140 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R
R

th j-mb

th j-a

Thermal resistance junction to - - 1.1 K/W
mounting base
Thermal resistance junction to in free air 60 - K/W
ambient

February 1999 1 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOS

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V

(BR)GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

TM

transistor

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2 3.0 4.0 V

Tj = 175˚C 1 - - V

Tj = -55˚C - - 4.4 V

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.02 1 µA

Tj = 175˚C - - 20 µA
Gate-source breakdown IG = ±1 mA; 16 - - V
voltage
Drain-source on-state VGS = 10 V; ID = 25 A - 12 16 mΩ
resistance Tj = 175˚C - - 30 mΩ

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
C

C
C

Q
Q
Q

t
t
t
t

L

fs

iss
oss
rss

g(tot)
gs
gd

d on
r
d off
f

d

Forward transconductance VDS = 25 V; ID = 25 A 8 39 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2200 2900 pF

Output capacitance - 500 600 pF
Feedback capacitance - 200 270 pF

Total gate charge ID = 50 A; V

= 44 V; VGS = 10 V - - 85 nC

DD

Gate-source charge - - 19 nC
Gate-drain (Miller) charge - - 37 nC

Turn-on delay time VDD = 30 V; ID = 25 A; - 18 26 ns
Turn-on rise time VGS = 10 V; RG = 10 Ω - 3585ns
Turn-off delay time Resistive load - 45 60 ns
Turn-off fall time - 30 45 ns

Internal drain inductance Measured from contact screw on - 3.5 - nH

tab to centre of die

L

d

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

L

s

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

February 1999 2 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOS

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

TM

transistor

Continuous reverse drain - - 64 A
current
Pulsed reverse drain current - - 210 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 65 A; VGS = 0 V - 1.0 - V

Reverse recovery time IF = 65 A; -dIF/dt = 100 A/µs; - 57 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.14 - µC

Drain-source non-repetitive ID = 65 A; VDD ≤ 25 V; - - 200 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

February 1999 3 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N
TrenchMOS

1000

ID / A

RDS(ON) = VDS/ID

100

10

1

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

1E+01

1E+00

1E-01

1E-02

TM

transistor

SOAX514

tp =
1 us

10 us
100 us

DC

11055

VDS / V

Zth / (K/W)

0.5

0.2

0.1

0.05

0.02

0

P

D

1 ms

10 ms
100 ms

100

BUKX514-55

p

t

p

t

D =

T

t

T

RDS(ON)/mOhm

30

VGS/V = 6

25

20

15

10

5

0

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

p

100

ID/A

80

60

40

20

= f(ID); parameter V

DS(ON)

Tj/C = 175

6.5

7

8
9

10

ID/A

.

GS

25

1E-03

1E-07 1E-05 1E-03 1E-01 1E+01

t / s

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

100

16

ID/A

10

80

60

40

20

0

0246810

Fig.5. Typical output characteristics, Tj = 25 ˚C

8

7.5

VDS/V

VGS/V =

ID = f(VDS); parameter V

GS

7

6.5

6

5.5

5

4.5
4

.

0

0123456789

VGS/V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

40

gfs/S

35

30

25

20

15

10

5

0

0 20406080100

Fig.8. Typical transconductance, Tj = 25 ˚C

ID/A

.

gfs = f(ID); conditions: VDS = 25 V

j

February 1999 4 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N
TrenchMOS

a

2.5

2

1.5

1

0.5

-100 -50 0 50 100 150 200

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

5

max.

4

typ.

3

min.

2

1

TM

transistor

BUK959-60

Tmb / degC

= f(Tj); ID = 25 A; VGS = 5 V

Rds(on) normlised to 25degC

BUK759-60

4

3.5

3

2.5

2

Thousands (pF)

1.5

1

5

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

VDS/V

, C

iss

oss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

12

VGS/V

10

8

6

4

2

VDS = 14V

VDS = 44V

, C

rss

Ciss

Coss
Crss

.

0

-100 -50 0 50 100 150 200
Tj / C

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

012345

2%

Sub-Threshold Conduction

typ

98%

GS

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

0

0 102030405060

QG/nC

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 50 A; parameter V

GS

100

IF/A

80

60

Tj/C = 175 25

40

20

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS/V

DS

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

j

February 1999 5 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N
TrenchMOS

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140 160 180

Fig.15. Normalised avalanche energy rating.

W

TM

transistor

Tmb / C

% = f(Tmb); conditions: ID = 75 A

DSS

VDD

VGS

0

RD

VDS

RG

T.U.T.

Fig.17. Switching test circuit.

VDD

+

-

+

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅ LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

-

-ID/100

)

February 1999 6 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOS

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

TM

transistor

10,3
max

3,7

2,8

4,5

max

1,3

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

max

(2x)

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

123

0,9 max (3x)

2,54 2,54

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

0,6

2,4

February 1999 7 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ48N

TrenchMOS

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

TM

transistor

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

February 1999 8 Rev 1.000