Datasheet IRFZ44NS Datasheet (Philips)

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS
TrenchMOS

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a surface mounting V
plastic envelope using ’trench’I
technology.Thedevice features very P
low on-state resistance and has T
integral zener diodes giving ESD R
protectionupto 2kV. Itis intended for resistance VGS = 10 V
useinswitchedmodepowersupplies
and general purpose switching
applications.

PINNING - SOT404 (D2PAK) PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 gate
2 drain
3 source

mb drain

TM

transistor

DS

D

tot
j

DS(ON)

Drain-source voltage 55 V
Drain current (DC) 49 A
Total power dissipation 110 W
Junction temperature 175 ˚C
Drain-source on-state 22 mΩ

mb

g

2

13

d

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot

stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 20 V
Drain current (DC) Tmb = 25 ˚C - 49 A
Drain current (DC) Tmb = 100 ˚C - 35 A
Drain current (pulse peak value) Tmb = 25 ˚C - 160 A
Total power dissipation Tmb = 25 ˚C - 110 W
Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R
R

th j-mb

th j-a

Thermal resistance junction to - - 1.4 K/W
mounting base
Thermal resistance junction to Minimum footprint, FR4 50 - K/W
ambient board

February 1999 1 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS

TrenchMOS

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V

(BR)GSS

R

DS(ON)

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

t

d on

t

r

t

d off

t

f

L

d

L

s

TM

transistor

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V

Tj = 175˚C 1.0 - - V

Tj = -55˚C - - 4.4

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 175˚C - - 500 µA

Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.04 1 µA

Tj = 175˚C - - 20 µA
Gate source breakdown voltage IG = ±1 mA; 16 - - V
Drain-source on-state VGS = 10 V; ID = 25 A - 15 22 mΩ
resistance Tj = 175˚C - - 42 mΩ

Forward transconductance VDS = 25 V; ID = 25 A 6 - - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1350 1800 pF

Output capacitance - 330 400 pF
Feedback capacitance - 155 215 pF

Total gate charge VDD = 44 V; ID = 50 A; VGS = 10 V - - 62 nC
Gate-cource charge - - 15 nC
Gate-drain (miller) charge - - 26 nC

Turn-on delay time VDD = 30 V; ID = 25 A; - 18 26 ns
Turn-on rise time VGS = 10 V; RG = 10 Ω - 5075ns
Turn-off delay time Resistive load - 40 50 ns
Turn-off fall time - 30 40 ns

Internal drain inductance Measured from upper edge of drain - 2.5 - nH

tab to centre of die

Internal source inductance Measured from source lead - 7.5 - nH

soldering point to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

t

rr

Q

rr

February 1999 2 Rev 1.000

Continuous reverse drain - - 49 A
current
Pulsed reverse drain current - - 160 A
Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V

IF = 40 A; VGS = 0 V - 1.0 -

Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 47 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.15 - µC

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS

TrenchMOS

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Fig.1. Normalised power dissipation.

TM

transistor

Drain-source non-repetitive ID = 45 A; VDD ≤ 25 V; - - 110 mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

Normalised Power Derating

Tmb / C

1000

ID/A

RDS(ON) =VDS/ID

100

10

1

1 10 100

DC

VDS/V

tp =
1 us
10us

100 us

1 ms

10ms
100ms

Fig.3. Safe operating area. Tmb = 25 ˚C

PD% = 100⋅PD/P

D 25 ˚C

= f(Tmb)

ID & IDM = f(VDS); IDM single pulse; parameter t

p

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140 160 180

Normalised Current Derating

Tmb / C

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 10 V

D 25 ˚C

Zth/(K/W)

10

1

0.5

0.2

0.1

0.1

0.05

0.02

0.01

0

0.001
1E-06 0.0001 0.01 1 100

p

t

P

D

t/s

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

p

t

D =

T

t

T

February 1999 3 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS
TrenchMOS

100

16

ID/A

10

80

60

40

20

0

0246810

Fig.5. Typical output characteristics, Tj = 25 ˚C

RDS(ON)/mOhm

40

VGS/V =

TM

transistor

9

8.5

VDS/V

VGS/V =

ID = f(VDS); parameter V

GS

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

.

30

gfs/S

25

20

15

10

5

0

0 20406080100

Fig.8. Typical transconductance, Tj = 25 ˚C

ID/A

.

gfs = f(ID); conditions: VDS = 25 V

2.5

a

BUK959-60

Rds(on) normlised to 25degC

35

30

25

20

15

10

0 102030405060708090

6

6.5
7

8

9

10

ID/A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID); parameter V

ID/A

100

DS(ON)

80

60

40

20

Tj/C = 175 25

GS

2

1.5

1

0.5

-100 -50 0 50 100 150 200

.

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

VGS(TO) / V

5

max.

4

typ.

3

min.

2

1

Tmb / degC

= f(Tj); ID = 25 A; VGS = 10 V

BUK759-60

0

024681012

VGS/V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

j

0

-100 -50 0 50 100 150 200
Tj / C

Fig.10. Gate threshold voltage.

V

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

GS

February 1999 4 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS
TrenchMOS

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

012345

Fig.11. Sub-threshold drain current.

ID = f(V

2.5

2

1.5

Thousands pF

1

.5

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

TM

transistor

Sub-Threshold Conduction

2%

; conditions: Tj = 25 ˚C; VDS = V

GS)

typ

VDS/V

98%

, C

iss

oss

, C

GS

rss

Ciss

Coss

Crss

.

100

IF/A

80

60

Tj/C = 175 25

40

20

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

VSDS/V

Fig.14. Typical reverse diode current.

IF = f(V

120
110
100

90
80
70
60
50
40
30
20
10

0

); conditions: V

SDS

WDSS%

20 40 60 80 100 120 140 160 180

= 0 V; parameter T

GS

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 49 A

DSS

j

12

VGS/V

10

8

6

4

2

0

0 1020304050

VDS = 14V

VDS = 44V

QG/nC

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 50 A; parameter V

GS

DS

L

VDS

VGS

0

RGS

T.U.T.

Fig.16. Avalanche energy test circuit.

W

= 0.5 ⋅LI

DSS

2

D

⋅BV

DSS

/(BV

R 01

shunt

DSS−VDD

VDD

+

-

-ID/100

)

February 1999 5 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS
TrenchMOS

VGS

0

TM

transistor

RD

VDS

RG

T.U.T.

Fig.17. Switching test circuit.

VDD

+

-

February 1999 6 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS

TrenchMOS

MECHANICAL DATA

TM

transistor

Plastic single-ended package (Philips version of D2-PAK); 2 leads SOT404

A

E

D

1

D

H

D

A

1

L

p

c

Q

EUROPEAN

PROJECTION

ISSUE DATE

97-06-16

e e

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

mm

4.5

4.1

OUTLINE

VERSION

SOT404

b

1

1.40

0.85

1.27

0.60

IEC JEDEC EIAJ

0.64

0.46

9.65

8.65

D

D

1

1.6

10.3

1.2

REFERENCES

b

0 2.5 5 mm

scale

E

eLpHDQc

2.54

9.7

2.9

2.1

14.8

2.20

2.60

15.4

Fig.18. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

February 1999 7 Rev 1.000

Philips Semiconductors Product specification

N-channel enhancement mode IRFZ44NS

TrenchMOS

MOUNTING INSTRUCTIONS

Dimensions in mm

TM

transistor

11.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

February 1999 8 Rev 1.000