Datasheet IRFU9220, IRFR9220 Datasheet (Intersil)

IRFR9220, IRFU9220

Data Sheet July 1999

3.6A, 200V, 1.500 Ohm, P-Channel Power
MOSFETs

These are advancedpowerMOSFETsdesigned,tested,and
guaranteed to withstand a specific level of energy in the
avalanche breakdown mode of operation. These are
P-Channel enhancement-mode silicon gate power field­effecttransistors designed for applications such as switching
regulators, switching converters, motor drivers, relay drivers,
and drivers for high-power bipolar switching transistors
requiring high speed and low gate-drive power. These types
can be operated directly from integrated circuits.

Formerly developmental type TA17502.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFR9220 TO-252AA IF9220
IRFU9220 TO-251AA IF9220

NOTE: Whenorderinguse theentirepartnumber. Addthesuffix 9A
to obtain the TO-252AA variant in tape and reel, e.g., IRFR92209A.

File Number

Features

• 3.6A, 200V

DS(ON)

= 1.500Ω

®

Model

•r

• Temperature Compensating PSPICE

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

4015.3

Packaging

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN (FLANGE)

DRAIN (FLANGE)

4-89

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRFR9220, IRFU9220

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRFR9220, IRFU9220 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P

DSS

DGR

GS

DM

AS

D

Refer to Peak Current Curve

D

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

-200 V

-200 V
±20 V

3.6

Refer to UIS Curve

42

0.33

-55 to 150

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ= 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)ID

Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t
Total Gate Charge Q

g(TOT)VGS

Gate to Drain Charge Q
Gate to Source Charge Q

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

DSSID

DSS

GSSVGS

ON

r

f

OFF

gd
gs

ISSVDS
OSS
RSS

θJC

θJA

= 250µA, VGS = 0V -200 - - V

= VDS, ID = 250µA -2.0 - -4.0 V
VDS = Rated BV
VDS = 0.8 x Rated BV

, VGS = 0V - - -25 µA

DSS

, VGS = 0V, TC = 150oC - - -250 µA

DSS

= ±20V - - ±100 nA

= 2.2A, VGS = -10V (Figure 9) - - 1.500 W

VDD = -100V, ID = 3.9A,
RL = 24Ω, VGS = -10V,
RGS = 18Ω
(Figures 13, 16, 17)

- - 50 ns

- 8.8 - ns

-27- ns

- 7.3 - ns

-19- ns

- - 50 ns

= 0 to -10V VDD = -160V,

ID = 3.9A,
RL = 41Ω
I

G(REF)

= -25V, VGS = 0V, f = 1MHz
(Figure 12)

= 1.45mA

-20- nC

-11- nC

- 3.3 - nC

- 550 - pF

- 110 - pF

-33- pF

- - 3.00oC/W

- - 100

o

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage (Note 2) V
Diode Reverse Recovery Time t
Reverse Recovery Charge Q

SDISD

rr

RR

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4-90

= -3.6A - - -6.3 V

ISD = -3.6A, dISD/dt = -100A/µs - 150 300 ns

0.97 2.0 µC

IRFR9220, IRFU9220

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

FIGURE 1. NORMALIZEDPOWER DISSIPATION vs CASE

TEMPERATURE

10

-4

-3

-2

, DRAIN CURRENT (A)

-1

D

I

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.5

1

0.2

0.1

0.05

0.1

0.02

0.01

, TRANSIENT THERMAL IMPEDANCE

JC

θ

Z

0.01
10

-20

-10

-1

, DRAIN CURRENT (A)

D

I

TC = 25oC

= MAX RATED

T

J

-0.1

-1 -10 -100

SINGLE PULSE

-5

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

VDS, DRAIN TO SOURCE VOLTAGE (V)

-4

10

DS(ON)

V

DSS

-3

10

t1, RECTANGULAR PULSE DURATION (s)

-2

10

-1

10

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

-50

MAX = -200V

100µs

1ms

10ms

100ms
DC

-500

VGS = -20V

-10

VGS = -10V

, PEAK CURRENT CAPABILITY (A)

DM

I

-1

-5

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

10

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t
PEAK TJ= PDM x Z

FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:

-3

10

10

t, PULSE WIDTH (s)

1/t2

+ T

JC

θ

0

10

150 T



=

II

-2

-----------------------



25



-1

10

C

–

125

C

TC = 25oC

1

10

0

10

1

10

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

4-91

IRFR9220, IRFU9220

Typical Performance Curves

-10

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

If R = 0

= (L) (IAS) / (1.3 RATED BV

t

AS

AV

I

If R

≠ 0

= (L/R) ln [(IAS*R) / (1.3 RATED BV

t

AV

-1

0.01 0.1 1
t

, TIME IN AVALANCHE (ms)

AV

DSS

- VDD)

Unless Otherwise Specified (Continued)

STARTING TJ = 25oC

- VDD) + 1]

DSS

10

-5

-4
VGS = -20V

-3

-2

, DRAIN CURRENT (A)

D

I

-1

0

0

-1.5 -3.0 -4.5 -6.0 -7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = -10V

VGS = -8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T

C

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS

-8

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V

-6

-4

-2

, DRAIN TO SOURCE CURRENT (A)

0

DS(ON)

I

0-1-2-3-4-5

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC

25oC

150oC

-6 -7

2.5

PULSE DURATION = 80µs
V

= -10V

GS

I

= -2.2A

D

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

VGS = -7V

VGS = -6V

= 25oC

VGS = -5V

VGS = -4.5V

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

2.0
VGS = VDS, ID = 250µA

1.5

1.0

NORMALIZED GATE

0.5

THRESHOLD VOLTAGE

0

-80 -40 0 40 80 160120
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

TEMPERATURE

4-92

RESISTANCE vs JUNCTION TEMPERATURE

2.0
ID = 250µA

1.5

1.0

0.5

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs TEMPERATURE

IRFR9220, IRFU9220

Typical Performance Curves

700

Unless Otherwise Specified (Continued)

-200

VDD = BV

DSS

VDD = BV

DSS

600

C

C

ISS

OSS

VGS= 0V, f = 1MHz
C

= CGS + C

ISS

C

= C

RSS

C

≈ CDS+ C

OSS

500

400

300

200

C, CAPACITANCE (pF)

100

C

0

RSS

0 -5 -10 -15 -20 -25

VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

GD

GD

-160

-120

-80

-40

, DRAIN TO SOURCE VOLTAGE (V)

DS

V

0

20

I

G(REF)

I

G(ACT)

RL = 51Ω
I

G(REF)

V

GS

0.75 BV

0.50 BV

0.25 BV

= -1.45mA

= -10V

0.75 BV

DSS

0.50 BV

DSS

0.25 BV

DSS

t, TIME (µs)

DSS
DSS
DSS

80

I

G(REF)

I

G(ACT)

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Application Notes AN7254 and AN7260.

FIGURE 13. NORMALIZEDSWITCHINGWAVEFORMSFOR

CONSTANT GATE CURRENT

Test Circuits and Waveforms

V

DS

L

0

t

AV

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

, GATE TO SOURCE VOLTAGE (V)

GS

V

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V
V

GS

t

P

AS

R

G

DUT

I

AS

0.01Ω

-

V

DD

+

V

DD

I

AS

t

P

BV

DSS

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

t

ON

t

d(ON)

t

R

L

DUT

R

V

GS

G

-

V

DD

+

0

V

DS

V

GS

0

10%

r

10%

90%

50%

PULSE WIDTH

t

d(OFF)

V

90%

DS

t

OFF

50%

90%

t

f

10%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

4-93

IRFR9220, IRFU9220

Test Circuits and Waveforms

CURRENT

REGULATOR

12V

BATTERY

0

0.2µF

I

g(REF)

50kΩ

0.3µF

G

IG CURRENT

SAMPLING

RESISTOR RESISTOR

FIGURE 18. GATE CHARGE TEST CIRCUIT

(Continued)

-V

DS

(ISOLATED
SUPPLY)

DUT

D

DUT

S

CURRENT

I

D

SAMPLING

+V

DS

0

V

DS

Q

gs

V

DD

0

I

g(REF)

Q

gd

Q

g(TOT)

V

GS

FIGURE 19. GATE CHARGE WAVEFORMS

4-94

PSPICE Electrical Model

.SUBCKT IRFU9220 2 1 3 REV 9/6/94

CA 12 8 723e-12
CB 15 14 733e-12
CIN 6 8 517e-12

DBODY 5 7 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD

EBREAK 7 11 17 18 -244.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1

IT 8 17 1

LDRAIN 2 5 1e-9
LGATE 1 9 2.609e-9
LSOURCE 3 7 2.609e-9

MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01

RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1.194
RGATE 9 20 2.17
RIN 6 8 1e9
RLDRAIN 2 5 10
RLGATE 1 9 26.09
RLSOURCE 3 7 26.09
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 90.1e-3
RVTO 18 19 RVTOMOD 1

RLGATE

GATE

1

LGATE

IRFR9220, IRFU9220

10

-

6

ESG

8

+

RGATE

EVTO

+

-

18

8

209

S1A S2A

12 15

CA

6

RIN

13

14

8

13

S2BS1B

13

+

6
8

-

DPLCAP

VTO

-

EDSEGS

+

CIN

CB

RLDRAIN

5

RSCL1RSCL2

51

+

5

51

50
RDRAIN

16

MOS1

14

+

5
8

-

ESCL

21

8

DBREAK

EBREAK

MOS2

RSOURCE

11

17
18

LDRAIN

+

-

RLSOURCE

7

LSOURCE

RBREAK

IT

DBODY

1817

RVTO

19

-

+

VBAT

DRAIN
2

3
SOURCE

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 -0.77

ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/4.6,6))}

.MODEL DBDMOD D (IS=2.56e-14 RS=8.09e-2 TRS1=-2.45e-3 TRS2=-1.33e-5 CJO=4.21e-10 TT=1.17e-7)
.MODEL DBKMOD D (RS=5.07 TRS1=-1.05e-3 TRS2=1.28e-5)
.MODEL DPLCAPMOD D (CJO=170e-12 IS=1e-30 N=10)
.MODEL MOSMOD PMOS (VTO=-3.58 KP=1.38 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.1e-3 TC2=-2.73e-6)
.MODEL RDSMOD RES (TC1=6.95e-3 TC2=2.23e-5)
.MODEL RSCLMOD RES (TC1=2.40e-3 TC2=-1.5e-5)
.MODEL RVTOMOD RES (TC1=-3.27e-3 TC2=-1.33e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=5.29 VOFF=3.29)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.29 VOFF=5.29)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-4.9)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.9 VOFF=0.1)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A NewPSPICESub-Circuit for thePower MOSFET FeaturingGlobalTemperature
Options; written by William J. Hepp and C. Frank Wheatley.

4-95

IRFR9220, IRFU9220

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.IntersilCorporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howev er, no responsibility is assumed by Intersil or its subsidiaries for its use; nor foranyinfringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-96

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