Datasheet IRFU320, IRFR320 Datasheet (Intersil)

Page 1

IRFR320, IRFU320

Data Sheet July 1999

3.1A, 400V, 1.800 Ohm, N-Channel Power MOSFETs

These are N-Channel enhancement mode silicon gate power ﬁeld effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a speciﬁed level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.

Formerly developmental type TA17404.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFR320 TO-252AA IFR320 IRFU320 TO-251AA IFU320

NOTE: When ordering, use the entire part number.Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e., IRFR3209A.

File Number

Features

• 3.1A, 400V

DS(ON)

= 1.800Ω

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

2412.3

Packaging

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

DRAIN (FLANGE)

GATE

DRAIN

SOURCE

DRAIN

(FLANGE)

4-395

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

Page 2

IRFR320, IRFU320

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Speciﬁed

IRFR320, IRFU320 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

D D

400 V 400 V

3.1

2.0 12 A

±20 V

50 W

A A

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

pkg

190 mJ

-55 to 150

300 260

NOTE:

1. TJ= 25oC to 125oC.

Electrical Speciﬁcations T

= 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV Gate Threshold Voltage V Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2) I

DSSID

GS(TH)VGS

DSS

D(ON)VDS

= 250µA, VGS = 0V, (Figure 10) 400 - - V

= VDS, ID = 250µA 2.0 - 4.0 V

VDS = Rated BV

= 0.8 x Rated BV

> I

D(ON)

, VGS = 0V - - 25 µA

DSS

, VGS = 0V, TJ = 125oC - - 250 µA

DSS

x r

DS(ON)MAX

, VGS = 10V,

3.1 - - A

(Figure 7) Gate to Source Leakage Current I Drain to Source On Resistance (Note 2) r

DS(ON)ID

Forward Transconductance (Note 2) g Turn-On Delay Time t

d(ON)VDD

Rise Time t Turn-Off Delay Time t

d(OFF)

Fall Time t Total Gate Charge

g(TOT)VGS

(Gate to Source + Gate to Drain) Gate to Source Charge Q Gate to Drain “Miller” Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Internal Drain Inductance L

Internal Source Inductance L

Thermal Resistance, Junction to Case R Thermal Resistance, Junction to Ambient R

GSS

VGS = ±20V - - ±100 nA

= 1.7A, VGS = 10V, (Figures 8, 9) - 1.600 1.800 Ω

VDS≥ 10V, ID = 2.0A, (Figure 12) 1.7 2.6 - S

= 200V, ID≈ 3.1A, RGS = 18Ω, RL = 63Ω,

VGS = 10V

MOSFET Switching Times are Essentially Indepen-

dent of Operating Temperature

= 10V, ID = 3.1A, VDS = 0.8 x Rated BV

= 1.5mA, (Figure 14)

G(REF)

Gate Charge is Essentially Independent of Operat-

ing Temperature

VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) - 350 - pF

ISS OSS RSS

Measured From the Drain

Lead, 6.0mm (0.25in) from Package to Center of Die

Measured From the

Modified MOSFET Symbol Showing the Internal Device Inductances

Source Lead, 6.0mm (0.25in) from Package to Source Bonding Pad

θJC

Typical Solder Mount - - 110oC/W

θJA

DSS,

-1015ns

-1421ns

-3045ns

-1320ns

-1320nC

- 2.2 3.3 nC

- 7.2 11 nC

-64-pF

- 8.1 - pF

- 4.5 - nH

- 7.5 - nH

- - 2.5oC/W

4-396

Page 3

IRFR320, IRFU320

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I Pulse Source to Drain Current

SDM

(Note 3)

Source to Drain Diode Voltage (Note 2) V

Reverse Recovery Time t Reverse Recovery Charge Q

NOTES:

2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD= 50V, starting TJ= 25oC, L = 3.1mH, RGS= 25Ω, peak IAS= 3.1A.

Modified MOSFET Symbol Showing the Integral Reverse P-N

- - 3.1 A

- - 12 A

Junction Rectifier

TJ = 25oC, ISD = 3.1A, VGS = 0V,

- - 1.6 V

(Figure 13) TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/µs 120 270 600 ns

TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/µs 0.64 1.4 3.0 µC

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

25 50 75 100

, CASE TEMPERATURE (oC)

Unless Otherwise Speciﬁed

125

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

0.5

0.2

0.1

0.05

0.02

0.1

0.01

-2

-5

SINGLE PULSE

-4

, TRANSIENT THERMAL IMPEDANCE

θJC

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

4.0

3.2

2.4

1.6

, DRAIN CURRENT (A)

0.8

150

175

25 75 125

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

-3

t1, RECTANGULAR PULSE DURATION (s)

-2

50 100

TC, CASE TEMPERATURE (oC)

CASE TEMPERATURE

θJC

1/t2

x R

θJC

NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z

0.1 1 10

+ T

150

4-397

Page 4

IRFR320, IRFU320

Typical Performance Curves

100

, DRAIN CURRENT (A)

0.1

OPERATION IN THIS AREA IS LIMITED BY r

DS(ON)

TJ = MAX RATED T

= 25oC

SINGLE PULSE

101

VDS, DRAIN TO SOURCE VOLTAGE (V)

Unless Otherwise Speciﬁed (Continued)

10µs

100µs

1ms

10ms

100

1000

VGS = 10V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

, DRAIN CURRENT (A)

0 40 80 120 160

VGS = 4.0V

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

VGS = 10V

VGS = 6.0V

VGS = 5.5V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

≥ 350V

VGS = 6.0V

VGS = 5.5V

VGS = 5.0V

VGS = 4.5V

200

, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 5.0V

VGS = 4.0V

69 15

VGS = 4.5V

TJ = 150oC

0.1

, DRAIN CURRENT (A)

-2

02468

, GATE TO SOURCE VOLTAGE (V)

TJ = 25oC

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

, DRAIN TO SOURCE

ON RESISTANCE

DS(ON)

0 3 6 9 12 15

, DRAIN CURRENT (A)

VGS = 10V

VGS = 20V

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= 10V, ID = 1.7A

2.4

1.8

1.2

ON RESISTANCE

0.6

NORMALIZED DRAIN TO SOURCE

-40 0 40 , JUNCTION TEMPERATURE (oC)

120

160

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

4-398

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Page 5

IRFR320, IRFU320

Typical Performance Curves

1.25 ID = 250µA

1.15

1.05

0.95

BREAKDOWN VOLTAGE

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-40 0 40 , JUNCTION TEMPERATURE (oC)

Unless Otherwise Speciﬁed (Continued)

120

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

160

750

600

ISS

450

OSS

300

C, CAPACITANCE (pF)

150

12 5102 5

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS= 0V, f = 1MHz C

= CGS + C C C

ISS RSS OSS

= C

≈ C

+ C

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

100

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 0V

, TRANSCONDUCTANCE (S)

01234 5

, DRAIN CURRENT (A)

TJ = 25oC

TJ = 150oC

, SOURCE TO DRAIN CURRENT (A)

0.1 0 0.3 0.6 0.9 1.2

, SOURCE TO DRAIN VOLTAGE (V)

TJ = 25oC

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

ID = 3.1A

= 320V

, GATE TO SOURCE (V)

VDS = 200V V

= 80V

1.5

4-399

048121620

, TOTAL GATE CHARGE (nC)

G(TOT)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Page 6

IRFR320, IRFU320

Test Circuits and Waveforms

DSS

VARY t

TO OBTAIN

REQUIRED PEAK I

DUT

0.01Ω

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

d(ON)

90%

10%

DUT

10%

50%

PULSE WIDTH

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

12V

BATTERY

0.2µF

50kΩ

G(REF)

CURRENT

REGULATOR

0.3µF

IG CURRENT

SAMPLING

RESISTOR RESISTOR

SAME TYPE AS DUT

DUT

CURRENT

SAMPLING

(ISOLATED SUPPLY)

g(TOT)

G(REF)

d(OFF)

90%

OFF

50%

90%

10%

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

4-400

Page 7

IRFR320, IRFU320

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-401

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