Datasheet IRFS3004TRL7PP Datasheet

Applications

)

l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

SOA

l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free

PD - 97378A

IRFS3004-7PPbF

HEXFET® Power MOSFET

D

V

DSS

R

DS(on

typ.

max.

G

I

D

(Silicon Limited)

I

S

D

(Package Limited)

D

40V

0.90m

1.25m
400A

240A

Ω
Ω

c

S

S

S

S

S

G

D2Pak 7 Pin

GDS

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

D

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)

I

D

I

DM

PD @TC = 25°C

V

GS

dv/dt
T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

d

f

Max.

c

400

c

280

240

1610

380

2.5

± 20

2.0

-55 to + 175

300

Avalanche Characteristics

d

e

290

See Fig. 14, 15, 22a, 22b

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

d

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

θ

JC

R

θ

JA

Junction-to-Case

Junction-to-Ambient (PCB Mount)

kl

j

–––

––– 40

0.40 °C/W

A

W

W/°C

V

V/ns

°C

mJ

A

mJ

www.irf.com 1

04/22/2010

IRFS3004-7PPbF

/

g

g

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

∆

V

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

fs Forward Transconductance 1300 ––– ––– S

Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

C

eff. (ER)

oss

C

eff. (TR)

oss

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Drain-to-Source Breakdown Voltage 40 ––– ––– V

∆

T

Breakdown Voltage Temp. Coefficient ––– 0.038 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 0.90 1.25
Gate Threshold Voltage 2.0 ––– 4.0 V
Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250
Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leaka

e ––– ––– -100

Internal Gate Resistance ––– 2.0 ––– Ω

Total Gate Charge ––– 160 240 nC
Gate-to-Source Charge ––– 42 –––
Gate-to-Drain ("Miller") Charge ––– 65 –––
Total Gate Charge Sync. (Qg - Qgd)

––– 95 –––
Turn-On Delay Time ––– 23 ––– ns
Rise Time ––– 240 –––
Turn-Off Delay Time ––– 91 –––
Fall Time ––– 160 –––
Input Capacitance ––– 9130 ––– pF
Output Capacitance ––– 2020 –––
Reverse Transfer Capacitance ––– 990 –––

––– 2590 –––

h

i

––– 2650 –––

400

c

Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)

Continuous Source Current ––– –––

(Body Diode)
Pulsed Source Current ––– ––– 1610 A

(Body Diode)

d

Diode Forward Voltage ––– ––– 1.3 V
Reverse Recovery Time ––– 49 ––– ns

––– 51 –––
Reverse Recovery Charge ––– 37 ––– nC

––– 41 –––
Reverse Recovery Current ––– 3.2 ––– A
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VGS = 0V, ID = 250µA
Reference to 25°C, I
VGS = 10V, ID = 195A

mΩ

VDS = VGS, ID = 250µA
V

= 40V, VGS = 0V

DS

V

= 40V, VGS = 0V, TJ = 125°C

DS

V

= 20V

GS

= -20V

V

GS

VDS = 10V, ID = 195A

= 180A

I

D

=20V

V

DS

= 10V

g

V

GS

I

= 180A, VDS =0V, VGS = 10V

D

VDD = 26V
I

= 240A

D

R

= 2.7Ω

G

VGS = 10V

g

VGS = 0V

= 25V

V

DS

ƒ = 1.0 MHz, See Fig. 5

= 0V, VDS = 0V to 32V i, See Fig. 11

V

GS

V

= 0V, VDS = 0V to 32V

GS

A

MOSFET symbol

showing the
integral reverse

p-n junction diode.

= 25°C, IS = 195A, VGS = 0V

T

J

= 25°C VR = 34V,

T

J

= 125°C IF = 240A

T

J

= 25°C

T

J

= 125°C

T

J

= 25°C

T

J

Conditions

= 5mA

D

g

Conditions

h

Conditions

di/dt = 100A/µs

d

D

G

S

g

g

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I
above this value .

, starting TJ = 25°C, L = 0.01mH

Jmax

= 240A, VGS =10V. Part not recommended for use

AS

 I

≤ 240A, di/dt ≤ 740A/µs, V

SD

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.
 C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

as C

 C

C

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

is rising from 0 to 80% V

DS

is rising from 0 to 80% V

DS

DSS

DSS

.

.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C.

θ

 R

value shown is at time zero.

θJC

2 www.irf.com

IRFS3004-7PPbF

1000

TOP 15V

)
A

(

100

t
n
e

r

r
u

C
e

c

r

10

u
o
S

­o

t

­n

i
a

r

1

D
,

D

I

4.5V

0.1

BOTTOM 4.5V

60µs PULSE WIDTH

≤

Tj = 25°C

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)
A

(

t

100

n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

D

I

10

1

TJ = 175°C

TJ = 25°C

V

= 25V

DS

≤60µs PULSE WIDTH

0.1
3 4 5 6 7 8

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

1000

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

)
A

(
t
n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,
I

100

D

4.5V

TOP 15V

BOTTOM 4.5V

60µs PULSE WIDTH

≤

Tj = 175°C

10

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.0

e
c
n
a

t
s

i
s
e

R
n
O
e

c

r
u
o
S

­o

t

­n

i
a

r
D

,

)
n
o

(
S
D

R

)
d
e
z

i

l
a

m

r
o

N

(

1.5

1.0

ID = 195A

V

= 10V

GS

0.5

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Junction Temperature (°C)

Fig 4. Normalized On-Resistance vs. Temperature

100000

)
F

10000

p

(
e

c
n
a

t

i
c
a
p
a

C

1000

,
C

100

V

= 0V, f = 1 MHZ

GS

C

= C

= C

= C

+ Cgd, C

gs

gd

+ C

ds

iss

C

rss

C

oss

C

iss

C

oss

C

rss

SHORTED

ds

gd

1 10 100

VDS, Drain-to-Source Voltage (V)

14.0
ID= 180A

12.0

)
V

(
e

g

10.0

a

t

l
o
V

e

8.0

c

r
u
o
S

-

6.0

o

t

­e

t
a

4.0

G
,

S
G

V

2.0

VDS= 32V

VDS= 20V

0.0
0 50 100 150 200 250

QG, Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFS3004-7PPbF

)
A

(
t
n
e

r

r
u

C
n

i
a

r
D
e

s

r
e
v
e

R
,

I

1000

TJ = 175°C

100

10

1

D
S

0.1

0.0 0.5 1.0 1.5 2.0

VSD, Source-to-Drain Voltage (V)

TJ = 25°C

Fig 7. Typical Source-Drain Diode

Forward Voltage

420

360

)

300

A

(
t
n
e

r

240

r
u

C
n

i

180

a

r
D
,

D

120

I

60

0

25 50 75 100 125 150 175

TC , Case Temperature (°C)

Limited By Package

Fig 9. Maximum Drain Current vs.

V

GS

= 0V

10000

OPERATION IN THIS AREA

)
A

(
t

1000

n
e

r

r
u

C
e

c

r
u

100

o
S

­o

t

­n

i
a

r
D

10

,

D

I

Tc = 25°C
Tj = 175°C
Single Pulse

1

0 1 10 100

LIMITED BY RDS(on)

100µsec

1msec

10msec

DC

VDS, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

)
V

(

50

e
g
a

t

l
o
V

n
w

o
d
k
a
e

r
B

e
c

r
u
o
S

­o

t

­n

i
a

r
D

,

S
S
D

)
R
B

(

V

Id = 5mA

48

46

44

42

40

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

Fig 10. Drain-to-Source Breakdown Voltage

Case Temperature

3.5

3.0

2.5

)
J

2.0

µ

(
y

g

r
e

1.5

n
E

1.0

0.5

0.0

-5 0 5 10 15 20 25 30 35 40 45

V

Drain-to-Source Voltage (V)

DS,

Fig 11. Typical C

Stored Energy

OSS

1200

)
J

m

(
y

1000

g

r
e
n
E

e

800

h
c
n
a

l
a
v

600

A
e

s

l
u
P

400

e

l
g
n

i
S
,

200

S
A

E

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

TOP 44A

BOTTOM 240A

I

D

80A

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

4 www.irf.com

IRFS3004-7PPbF

τ

1

W

/
C

°
)

C
J
h

t

Z
(

e
s
n
o
p
s
e

0.01

R
l
a

m

r
e
h
T

0.001

1000

D = 0.50

0.1

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE
( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

R

R

R

1

2

R

1

τ

2

τ

3

R

R

2

3

τ

3

τ

2

3

Ri (°C/W) τi (sec)

4

R

4

0.00757 0.000006

τ

C

τ

0.06508 0.000064

4

τ

4

0.18313 0.001511

0.14378 0.009800

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

)
A

(
t
n
e

r

r
u

C
e

h
c
n
a

l
a
v
A

100

10

0.01

0.05

0.10

pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and

Tstart = 150°C.

1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

320

TOP Single Pulse

280

)
J

m

240

(
y

g

r
e

200

n
E

e
h

160

c
n
a

l
a

120

v
A
,

R

80

A

E

BOTTOM 1.0% Duty Cycle
ID = 240A

40

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

2. Safe operation in Avalanche is allowed as long asT

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase

. This is validated for every part type.

jmax

is not exceeded.

jmax

= Average power dissipation per single avalanche pulse.

during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15).
t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t
Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFS3004-7PPbF

4.5

)
V

4.0

(
e

g
a

t

l

3.5

o
V

d

l
o

3.0

h
s
e

r
h

t

2.5

e

t
a

G
,

)
h

t

(
S
G

V

ID = 250µA

ID = 1.0mA

2.0
ID = 1.0A

1.5

1.0

-75 -50 -25 0 25 50 75 100 125 150 175 200

TJ , Temperature ( °C )

Fig 16. Threshold Voltage vs. Temperature

12

IF = 144A

11

VR = 34V

10

TJ = 25°C

9

TJ = 125°C

)

8

A

(

7

M
R
R

I

6

5

4

3

2

100 200 300 400 500

diF /dt (A/µs)

10

IF = 96A

9

VR = 34V

TJ = 25°C

8

TJ = 125°C

7

)
A

(

6

M
R
R

I

5

4

3

2

100 200 300 400 500

diF /dt (A/µs)

Fig. 17 - Typical Recovery Current vs. dif/dt

140

IF = 96A

VR = 34V

120

TJ = 25°C

TJ = 125°C

100

)
C

n

(

80

R
R

Q

60

40

20

100 200 300 400 500

diF /dt (A/µs)

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

180

IF = 144A

160

VR = 34V

TJ = 25°C

140

TJ = 125°C

120

)
C

n

(

100

R
R

Q

80

60

40

20

100 200 300 400 500

diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFS3004-7PPbF

A

+

-

+

-





Reverse
Recovery
Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance
Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

V

DD

Re-Applied
Voltage

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

G

V

20V

GS

Fig 22a. Unclamped Inductive Test Circuit

V

GS

R

G

10V

V

GS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

D.U.T

I

AS

Ω

0.01

t

p

+

V

DD

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

R

V

DS

D

V

DS

90%

D.U.T.

V

DD

10%
V

GS

t

d(on)tr

t

d(off)tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms

Current Regulator

Same Type as D.U.T.

.2µF

12V

V

GS

50KΩ

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

+

V

DS

-

I

D

Vds

Vgs(th)

Qgs1

Qgs2 Qgd Qgodr

Id

Vgs

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

Fig 24b. Gate Charge Waveform

IRFS3004-7PPbF

D2Pak - 7 Pin Package Outline

Dimensions are shown in millimeters (inches)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com

D2Pak - 7 Pin Part Marking Information

14

2

D

Pak - 7 Pin Tape and Reel

IRFS3004-7PPbF

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information. 04/2010

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