Datasheet IRFR7446PBF Datasheet

Applications

R

DS(on)

typ.

Ω

l Brushed Motor drive applications l BLDC Motor drive applications l PWM Inverterized topologies l Battery powered circuits

l Half-bridge and full-bridge topologies l Synchronous rectifier applications l Resonant mode power supplies l OR-ing and redundant power switches l DC/DC and AC/DC converters

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

SOA

l Enhanced body diode dv/dt and dI/dt Capability l Lead-Free

S trongIRFET

IRFR7446PbF

HEXFET® Power MOSFET

D

V

DSS

G

GDS

Gate Drain Source

max. I

D

(Silicon Limited)

S

I

D

(Package Limited)

D

IRFR7446TRPbF

S

G

D-Pak

40V

3.0m

3.9m

120A

56A

c

Ordering Information

Orderable part number Package Type Standard Pack

Form Quantity

IRFR7446PBF D-PAK Tube/Bulk 75 IRFR7446PBF IRFR7446TRPBF D-PAK Tape and Reel 2000 IRFR7446TRPBF

)

Ω

10

(

m e

c n a

t s

i s

8

e R n O e

c

r

6

u o S

o

t

n

i a

r

4

D ,

) n o

(

S D

2

R

4 8 12 16 20

VGS, Gate-to-Source Voltage (V)

TJ = 125°C

TJ = 25°C

ID = 56A

120

100

) A

( t

80

n e

r

r u

C

60

n

i a

r D

40

,

D

I

20

0

25 50 75 100 125 150 175

TC, Case Temperature (°C)

Complete Part Number

LIMITED BY PACKAGE

Fig 1. Typical On-Resistance vs. Gate Voltage

Fig 2. Maximum Drain Current vs. Case Temperature

IRFR7446PbF

Absolute Maximum Ratings

Symbol Parameter Units

I

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

D

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

D

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wir e Bond Limi t ed)

I

D

I

DM

Pulsed Drain Current

d

PD @TC = 25°C Maximum Power Dissipation W

Linear Derating Factor W/°C

V

GS

T

J

T

STG

Gate-to- Source Voltage V

Operating J unction and

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

Avalanche Characteristics

E

AS (T herma lly limited)

E

AS (T herma lly limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

d

Repetitive Avalanche Energy

e

l

d

See Fig 15,16, 23a, 23b

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

θJA

R

θJA

Junct ion-to-Case

Junct ion-to-Ambient (PCB Mount)

Junct ion-to-Ambient

k

j

k

––– 1.52

––– 50

––– 110

Max.

c

120

c

84

56

520

98

0.66

± 20

-55 to + 175

300

125

251

°C

mJ

°C/W

A

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

R

DS(on)

(BR)DSS

/ΔT

J

Drain-to-Source Breakdown Voltage 40 ––– ––– V

Breakdown Voltage Temp. Coefficient ––– 26 ––– mV/°C

Static Drain-to- Source On-Resistance ––– 3. 0 3.9 mΩ

4.4 ––– m

V

I

GS(th)

DSS

Gate Threshold Voltage 2.2 3.0 3.9 V

Drain-to-Source Leakage Current ––– ––– 1.0 μA

––– ––– 150

I

GSS

Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Revers e Leakage ––– ––– -100

R

G

Internal Gate Resistance ––– 1.5 ––– Ω

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140)

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 50Ω, I

 I

≤ 100A, di/dt ≤ 1306A/μs, V

SD

, starting TJ = 25°C, L = 0.08mH

Jmax

= 56A, VGS =10V.

AS

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

 Pulse width ≤ 400μs; duty cycle ≤ 2%.  C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

as C

while V

oss

 C

eff. (ER) is a fixed capacitance that gives the same energy as

oss

C

while V

oss

DS

is rising from 0 to 80% V

DS

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C.

θ

 Limited by T

* L

and LS are Internal Drain Inductance and Internal Source Inductance

D

Jmax

Conditions

= 0V, ID = 250μA

V

GS

Reference to 25°C, ID = 1mA

V

= 10V, ID = 56A

GS

V

Ω

= 6.0V, ID = 28A

GS

VDS = VGS, ID = 100μA

VDS = 40V, VGS = 0V

V

= 40V, VGS = 0V, TJ = 125°C

DS

= 20V

V

GS

V

= -20V

GS

is rising from 0 to 80% V

DSS

.

starting TJ = 25°C, L= 1mH, RG = 50Ω, I

d

g

= 22A, VGS =10V.

AS

Dynamic @ TJ = 25°C (unless otherwise specified)

di/dt = 100A/μs

g

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

*

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 170 ––– ––– S Q Q Q

Q t

d(on)

t

r

t

d(off)

t

f

C C C C C

g

gs

gd

sync

iss

oss

rss

oss

eff. (ER) eff. (TR)

Total Gate Charge ––– 65 130 nC Gate-to-Source Charge ––– 18 ––– Gate-to-Drain ("Miller") Charge ––– 22 ––– Total Gate Charge Sync. (Qg - Qgd)

––– 43 ––– Turn-On Delay Time ––– 9.8 ––– ns Rise Time ––– 13 ––– Turn-Off Delay Time ––– 32 ––– Fall Time ––– 20 ––– Input Capacitance ––– 3150 ––– pF

Output Capacitance ––– 480 ––– Reverse Transfer Capacitance ––– 330 –––

Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)

––– 570 –––

––– 680 –––

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

dv/dt t

rr

Q

rr

I

RRM

t

on

Continuous Source Current ––– –––

120

c

(Body Diode) Pulsed Source Current ––– ––– 480 A

(Body Diode)

d

Diode Forward Voltage ––– 0.9 1.3 V

Peak Diode Recovery

f

––– 4.8 ––– V/ns Reverse Recovery Time ––– 20 ––– ns

––– 21 ––– Reverse Recovery Charge ––– 13 ––– nC

––– 13 ––– Reverse Recovery Current ––– 1.8 ––– A

Forward Turn-On Time

IRFR7446PbF

Conditions

VDS = 10V, ID = 56A I

=56A

D

V

=20V

DS

VGS = 10V

= 56A, VDS =0V, VGS = 10V

I

D

VDD = 20V

= 30A

I

D

R

G

VGS = 10V VGS = 0V

V

DS

ƒ = 1.0 MHz, See Fig. 5 V

GS

V

GS

A

MOSFET symbol

showing the integral reverse

p-n junction diode. TJ = 25°C, IS = 56A, VGS = 0V

= 175°C, IS = 56A, VDS = 40V

T

J

= 25°C VR = 34V,

T

J

T

= 125°C IF = 56A

J

= 25°C

T

J

= 125°C

T

J

= 25°C

T

J

g

= 2.7

Ω

g

= 25V

= 0V, VDS = 0V to 32V i See Fig. 12 = 0V, VDS = 0V to 32V

Conditions

h

D

G

S

g

IRFR7446PbF

1000

) A

( t n

100

e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r D

1

,

D

I

4.3V

TOP 15V

BOTTOM 4.3V

≤ 60μs PULSE WIDTH Tj = 25°C

0.1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 3. Typical Output Characteristics

1000

) A

( t n

100

e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r

1

D ,

D

I

0.1

TJ = 175°C

TJ = 25°C

V

= 10V

DS

≤

60μs PULSE WIDTH

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

VGS

10V

7.0V

6.0V

5.5V

5.0V

4.5V

1000

) A

( t n e

r

100

u C e

c

r u o S

o

t

n

10

i a

r D

,

D

I

4.3V

TOP 15V

BOTTOM 4.3V

VGS

10V

7.0V

6.0V

5.5V

5.0V

4.5V

≤ 60μs PULSE WIDTH Tj = 175°C

1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 4. Typical Output Characteristics

2.0

e c n a

t s

i s e

R n O

)

e

d

c

r

e

u

z

i

l

o

a

S

-

m

o

r

t

-

o

n

i

N

(

a

r D

,

) n o

( S D

R

ID = 56A

V

= 10V

GS

1.5

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 5. Typical Transfer Characteristics

100000

) F p

10000

( e

c n a

t

i c a p a

C

1000

, C

100

V

= 0V, f = 1 MHZ

GS

C

= C

C

iss

rss

oss

= C

+ Cgd, C

gs

gd

+ C

ds

SHORTED

ds

gd

Ciss

Coss

Crss

1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 6. Normalized On-Resistance vs. Temperature

16

ID= 56A

) V

( e

g

12

a

t

l o V

e c

r u o

8

S

o

t

e

t a

G ,

4

S G

V

0

0 20 40 60 80 100

VDS= 32V

VDS= 20V

Q

Total Gate Charge (nC)

G

Fig 8. Typical Gate Charge vs. Gate-to-Source VoltageFig 7. Typical Capacitance vs. Drain-to-Source Voltage

IRFR7446PbF

1000

) A

( t

100

n e

r

r u

C n

i a

r D e

s

r e v e

R ,

D S

I

TJ = 175°C

10

TJ = 25°C

1

V

GS

0.1

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VSD, Source-to-Drain Voltage (V)

= 0V

Fig 9. Typical Source-Drain Diode

) V

(

49

e g a

t

l

48

o V

n

47

w o d k

46

a e

r B

45

e c

r u o

44

S

o

t

-

43

n

i a

r D

42

,

S S

41

D

) R B

(

40

V

-60 -40 -20 0 20 40 60 80 100120140160180

Forward Voltage

Id = 1.0mA

TJ , Temperature ( °C )

Fig 11. Drain-to-Source Breakdown Voltage

)

16.0

Ω

(

m e

c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D ,

) n o

(

S D

R

VGS = 5.5V

14.0 V

= 6.0V

GS

VGS = 7.0V

12.0 VGS = 8.0V VGS =10V

10.0

8.0

6.0

4.0

2.0 0 20 40 60 80 100 120 140 160 180 200

ID, Drain Current (A)

1000

) A

( t n

100

e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r D ,

D

I

OPERATION IN THIS AREA LIMITED BY RDS(on)

1

Tc = 25°C Tj = 175°C Single Pulse

0.1

0.1 1 10

imited by Package

L

VDS, Drain-toSource Voltage (V)

100μsec

1msec

Fig 10. Maximum Safe Operating Area

0.4

0.3

) J

μ

( y

0.2

g

r e n E

0.1

0.0

0 10 20 30 40

V

Drain-to-Source Voltage (V)

DS,

Fig 12. Typical C

Stored Energy

OSS

10msec

DC

Fig 13. Typical On-Resistance vs. Drain Current

IRFR7446PbF

10

W

/ C

°

1

)

C J h

t Z (

e s n o p s e

R l a

0.01

m

r e h T

0.001

)

A

(

t

n

e

r

u

C

e

h

c

n

a

l

a

v

A

0.1

100

10

D = 0.50

0.20

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and Tstart =25°C (Single Pulse)

1

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤj = 25°C and Tstart = 150°C.

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

140

TOP Single Pulse

120

) J

m

(

100

y g

r e n E

80

e h c n a

60

l a v A ,

40

R A

E

BOTTOM 1.0% Duty Cycle ID = 56A

20

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 14)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 16. Maximum Avalanche Energy vs. Temperature

IRFR7446PbF

4.5

) V

(

4.0

e g a

t

l o

3.5

V d

l o h s e

3.0

r h

t e

t a

G ) h

t

(

S G

V

ID =50μA

ID = 250μA

ID = 1.0mA

2.5

ID = 1.0A

2.0

1.5

-75 -50 -25 0 25 50 75 100 125 150 175

TJ , Temperature ( °C )

Fig 17. Threshold Voltage vs. Temperature

6

IF = 56A

VR = 34V

TJ = 25°C

TJ = 125°C

4

) A

(

M R R

I

2

6

IF = 34A

VR = 34V

TJ = 25°C

TJ = 125°C

4

) A

(

M R R

I

2

0

0 200 400 600 800 1000

diF /dt (A/μs)

Fig. 18 - Typical Recovery Current vs. dif/dt

80

IF = 34A

VR = 34V

TJ = 25°C

60

TJ = 125°C

) C

n

(

40

R R

Q

20

0

0 200 400 600 800 1000

diF /dt (A/μs)

80

IF = 56A

VR = 34V

TJ = 25°C

60

TJ = 125°C

) C

n

(

40

R R

Q

20

0

0 200 400 600 800 1000

Fig. 21 - Typical Stored Charge vs. dif/dt

0

0 200 400 600 800 1000

diF /dt (A/μs)

Fig. 20 - Typical Stored Charge vs. dif/dtFig. 19 - Typical Recovery Current vs. dif/dt

diF /dt (A/μs)

IRFR7446PbF

A

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf





Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer

-

• dv/dt controlled by R

• Driver same type as D.U.T.

• I

controlled by Duty Factor "D"

SD

• D.U.T. - Device Under Test



+

V

DD

G

+

-

Re-Applied Voltage

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

G

20V

V

GS

Fig 23a. Unclamped Inductive Test Circuit

V

GS

R

G

10V

V

GS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

D.U.T

I

AS

Ω

0.01

t

p

+

V

DD

-

I

AS

Fig 23b. Unclamped Inductive Waveforms

R

D.U.T.

D

+

V

DD

-

V

DS

Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms

Current Regulator

Same Type as D.U.T.

.2μF

12V

V

GS

50KΩ

3mA

.3μF

D.U.T.

+

V

DS

-

Vds

Vgs(th)

Id

Vgs

I

Current Sampling Resistors

Fig 25a. Gate Charge Test Circuit

I

G

D

Qgs1

Qgs2 Qgd Qgodr

Fig 25b. Gate Charge Waveform

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

IRFR7446PbF

D-Pak (TO-252AA) Part Marking Information

EXAMPLE:

Note: "P" in ass embly line position

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

THIS IS AN IRFR120 WI T H AS SE MB LY

LOT CODE 1234 ASS EMB LE D ON WW 16, 2001 IN THE ASSEMBLY LINE "A"

i ndi cates "L ead-F ree"

"P" in ass embly line position indicates "L ead-F r ee" qu ali fi cati on to th e cons umer-l evel

OR

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

IRF R120

12

PART NUMBER

IRF R120

116A

3412

PART NUMBER

DATE CODE P = DE S IGN AT E S L E AD- F R E E

34

P = DE S IGN AT E S L E AD- F R E E

YEAR 1 = 2001 WE EK 16 A = ASSEMBLY SITE CODE

DATE CODE YEAR 1 = 2001 WEEK 16 LINE A

PRODUCT (OPTIONAL)

PRODUCT QUALIFIED TO THE CONS UMER LE VEL (OPT IONAL)

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

IRFR7446PbF

TR

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

FEED DIRECTION

8.1 ( .318 )

7.9 ( .312 )

TRR

TRL

16.3 ( .641 )

15.7 ( .619 )

FEED DIRECTION

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

MS L 1

(per JEDEC JESD47F

guidelines)

Qualification information

Industrial

Qualification level

•

IRFR7446PbF

†

††

†††



RoHS compliant

D-PAK

Yes

(per JE DEC J-S T D-020D

†††

)

 Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/

 Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information:

http:www.irf.com/whoto-call/salesrep/

 Applicable version of JEDEC standard at the time of product release.

Revision History

Date Comment

1/6/2015

•

Updated E Updated note 10 “Limited by T

•

Updated package outline on page 9.

= 251mJ on page 2

AS (L =1mH)

, starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 22A, VGS =10V”. on page 2

Jmax

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/