Datasheet IRFR4104, IRFU4104 Datasheet (International Rectifier)

PD - 94728

Pulsed Drain C

c

Single Pul

gy

d

Single Pul

h

Aval

c

R

g

J

(PCB

i

AUTOMOTIVE MOSFET

IRFR4104 IRFU4104

HEXFET® Power MOSFET

Features

● Advanced Process Technology

● Ultra Low On-Resistance

● 175°C Operating Temperature

● Fast Switching

● Repetitive Avalanche Allowed up to Tjmax

G

Description

Specifically designed for Automotive applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.

Absolute Maximum Ratings

Parameter Units

(Silicon Limited)

ID @ TC = 25°C ID @ TC = 100°C

@ TC = 25°C

I

D

I

DM

PD @TC = 25°C

V

GS

E

AS (Thermally limited)

(Tested )

E

AS

I

AR

E

AR

T

J

T

STG

Contin uous Drain Current , V Contin uous Drain Current , V Contin uous Drain Current , V

urrent Power Dissipati on W Linear D er a t i ng Factor W/°C

Gate-to-Sour c e V o l tage V

se Avalanche Ener se Avalanche Energy Tested Value

anche Current

epetitive Avalanche Energy

Operat i n g J unction and Storag e Temperature Range °C

Soldering Temperature, for 10 seconds Mounting Torque , 6- 32 or M3 screw



@ 10V

GS

@ 10V

GS

@ 10V

GS

(Package Limited)

Thermal Resistance

Parameter Typ. Max. Units

R

JC

θ

R

JA

θ

R

JA

θ

Junction-to-Case ––– 1.05

unction-to-Ambient

Junction-to-Ambient ––– 110

mount)

HEXFET® is a registered trademark of International Rectifier.

www.irf.com 1

D

V

= 40V

DSS

R

S

®

D-Pak

IRFR4104

DS(on)

ID = 42A

= 5.5mΩ

I-Pak

IRFU4104

Max.

119

84

42 480 140

0.95

± 20

145 310

See Fig.12a, 12b, 15 , 16

-55 to + 175

300 (1. 6m m fr o m case )

y

in (1.1Nym)

10 lbf

––– 40 °C/W

mJ

A

7/17/03

IRFR/U4104

/

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V

(BR)DSS

∆

V

(BR)DSS

R

DS(on)

V

GS(th)

gfs Forwa rd Transconductance 58 ––– ––– S I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

C

oss

C

oss

C

eff.

oss

Source-Drain Ratings and Characteristics

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Drain-to-Sou rce Breakdown Vol tage 40 ––– ––– V

∆

T

Breakdown Voltag e Temp. Coef ficient ––– 0.032 ––– V/°C

J

Ω

Stat ic D r ai n- to-Sou rc e O n- R e s i s tance ––– 4.3 5.5

m

Gate Threshold Voltage 2.0 ––– 4.0 V

Drain-to-Sou rce Leaka ge Cu rr ent ––– ––– 20 µA

––– ––– 250 Gate-to-Sour c e Fo r w ard Leakage ––– ––– 200 nA Gate-to-Sour c e R ev erse Leak age ––– ––– -200 Total Gate Charge ––– 59 89 Gate-to-Sour c e C harge ––– 19 – –– nC Gate-to-Drai n ("Miller" ) Charge ––– 24 ––– Turn-On Delay Time ––– 17 ––– Rise Time ––– 69 ––– Turn-Off Delay Time ––– 37 ––– ns Fall Time ––– 36 ––– Internal Drain Inductance ––– 4.5 ––– Between lead,

nH 6mm (0.25in.)

Internal Source Inductance ––– 7.5 ––– from package

Input Capacitance ––– 2950 ––– Output Capacitance ––– 660 ––– Reverse Transf er C ap ac itance ––– 370 ––– pF Output Capacitance ––– 2130 ––– Output Capacitance ––– 590 ––– Effe c tive Out pu t Capacita nce ––– 850 –––

Paramete r Min . Typ. Max. Un its

Contin uous Source Cu rrent ––– ––– 42 (Body Diode) A

Pulsed Source Current ––– ––– 480 (Body Diode)

Diode Forward Voltage ––– ––– 1.3 V Reverse Recovery Time ––– 28 42 ns Reverse Recovery Charge ––– 24 36 nC Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

c

Conditions

VGS = 0V, ID = 250µA Referen ce to 25°C, I

= 10V, ID = 42A

V

GS

= 1mA

D

e

VDS = VGS, ID = 250µA

= 10V, ID = 42A

V

DS

= 40V, VGS = 0V

V

DS

= 40V, VGS = 0V, TJ = 125°C

V

DS

= 20V

V

GS

= -20V

V

GS

I

= 42A

D

= 32V

V

DS

VGS = 10V

e

VDD = 20V

= 42A

I

D

Ω

= 6.8

R

G

VGS = 10V

e

and center of die contact VGS = 0V

= 25V

V

DS

ƒ = 1.0MHz VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

= 0V, VDS = 32V, ƒ = 1. 0M Hz

V

GS

= 0V, VDS = 0V to 32V

V

GS

f

Conditions

MOSFET symbol showing the

integral reverse p-n junct ion diode.

T

= 25°C, IS = 42A, VGS = 0V

J

TJ = 25°C, IF = 42A, VDD = 20V di/dt = 100A/µs

e

2 www.irf.com

IRFR/U4104

1000

) A

(

t

n

e

r

100

u C e

c

r

u

o S

-

o

t

-

10

n

i

a

r D

,

D

I

4.5V 60µs PULSE WIDTH

Tj = 25°C

1

0.1 1 10 100

0 1 10 100

VDS, Drain-to-Sour ce Voltage (V)

1000

)

Α

(

t

n

e

r

100

u C e

c

r

u

o S

-

o

t

-

10

n

i

a

r D

,

D

I

TJ = 25°C

V

= 20V

DS

60µs PULSE WIDTH

1

4 6 8 10

VGS, Gate-to-Source Voltage (V)

V

TOP 15V 10V

7.0V

6.0V

5.5V

5.0V BOTTOM 4.5V

GS

8.0V

TJ = 175°C

1000

) A

(

t

n

e

r

100

u C e

c

r

u

o S

-

o

t

-

10

n

i

a

r D

,

D

I

4.5V

60µs PULSE WIDTH Tj = 175°C

1

0.1 1 10 100

0 1 10 100

VDS, Drain-to-Sour ce Voltage (V)

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

120

) S

(

100

e

c

n

a

t

c

80

u

d

n

o

c

s

60

n

a

r T

d

r

a

40

w

r

o F

,

s

20

f G

0

0 20406080100

ID, Drain-to-Source Current (A)

TJ = 175°C

TJ = 25°C

V

= 10V

DS

380µs PULSE WIDTH

V

TOP 15V 10V

7.0V

6.0V

5.5V

5.0V BOTTOM 4.5V

GS

8.0V

Fig 3. Typical Transfer Characteristics

Fig 4. Typical Forward Transconductance

Vs. Drain Current

www.irf.com 3

IRFR/U4104

5000

4000

) F

p

( e

3000

c

n

a

t

i

c

a

p

2000

a C

, C

1000

0

1 10 100

V

= 0V, f = 1 MHZ

GS

C

= C

Ciss

Coss Crss

+ Cgd, C

gs gd

+ C

ds

iss

C

rss

C

oss

VDS, Drain-to-Sour ce Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

1000.0

) A

(

t

100.0

n

e

r

u C n

i

a

r

10.0

D e

s

r

e

v

e R

,

1.0

D S

I

0.1

TJ = 175°C

TJ = 25°C

0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain V oltage (V)

20

SHORTED

ds

gd

) V

( e

g

a

t

l

o V

e

c

r

u

o S

-

o

t

-

e

t

a G

, V

ID= 42A

16

12

8

S

4

G

0

0 20406080100

Q

VDS= 32V VDS= 20V

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

10000

) A

1000

(

t

n

e

r

u C

100

e

c

r

u

o S

-

10

o

t

-

n

i

a

r D ,

1

D

I

V

= 0V

GS

Tc = 25°C Tj = 175°C Single Pulse

0.1 0 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

V

, Drain-toSource V oltage (V)

DS

100µsec

1msec

10msec

Fig 7. Typical Source-Drain Diode

Fig 8. Maximum Safe Operating Area

Forward Voltage

4 www.irf.com

120

τ

LIMITED BY PACKAGE

100

) A

(

80

t

n

e

r

u C

60

n

i

a

r D

,

40

D

I

20

0

25 50 75 100 125 150 175

TC , Case Temper ature (°C)

IRFR/U4104

2.0

e

c

n

a

t

s

i

s

e R n O e

)

c

d

r

e

u

z

i

o

l

S

a

-

m

o

t

r

-

o

n

i

N

(

a

r D

,

)

n

o

( S D

R

ID = 42A V

= 10V

GS

1.5

1.0

0.5

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

Fig 9. Maximum Drain Current Vs.

Case Temperature

10

)

C

1

J

h

t

Z (

e

s

n

o

p

s

e R

l

a m

r

e

h T

0.001

D = 0.50

0.20

0.1

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

1E-006 1E-005 0.0001 0.001 0.01 0.1

Fig 10. Normalized On-Resistance

Vs. Temperature

R

1

2

R

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

R

1

2

τ

2

τ

2

Ri (°C/W) τi (sec)

τ

C

0.5067 0.000414

0.5428 0.004081

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zt hjc + Tc

t1 , Rectangular Pulse Dur ation (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

www.irf.com 5

IRFR/U4104

A

15V

DRIVER

+

V

DD

-

R

20V

V

DS

G

GS

L

D.U.T

I

AS

Ω

0.01

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

10 V

Q

GS

Q

GD

600

)

J m

( y

500

g

r

e

n E

e

400

h

c

n

a

l

a

v

300

A e

s

l

u

200

P e

l

g

n

i S

100

, S A

E

0

25 50 75 100 125 150 175

I

TOP

13A

BOTTOM

Starting TJ, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

4.0

D

9.2A 42A

) V

V

G

Charge

Fig 13a. Basic Gate Charge Waveform

Current Regulator

Same Type as D.U.T.

50KΩ

.2µF

12V

V

GS

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

+

V

DS

-

I

D

Fig 13b. Gate Charge Test Circuit

( e

g

a

t

l

o

3.0

V d

l

o

h

s

e

r

h

t e

t

a

2.0

G

)

h

t

( S G

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

Fig 14. Threshold Voltage Vs. Temperature

6 www.irf.com

IRFR/U4104

1000

Duty Cycle = Singl e Pulse

Allowed avalanche Current vs

100

) A

(

t

n

e

r

u C

10

e

h

c

n

a

l

a

v A

1

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02

0.01

0.05

0.10

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

avalanche pulsewidth, tav assuming ∆Tj = 25°C due to

avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax

160

TOP Single Pulse

)

J m

120

( y

g

r

e

n E

e

h

80

c

n

a

l

a

v A

,

R

40

A

E

BOTTOM 1% Duty Cycle ID = 42A

Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T every part type.

2. Safe operation in Avalanche is allowed as long asT not exceeded.

. This is validated for

jmax

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P

avalanche pulse.

= Average power dissipation per single

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed

T

(assumed as 25°C in Figure 15, 16).

0

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Vs. Temperature

jmax

t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see figure 11)

thJC

P

= 1/2 ( 1.3·BV·Iav) = DT/ Z

D (ave)

I

2DT/ [1.3·BV·Zth]

av =

E

AS (AR)

= P

·f

av

D (ave)·tav

thJC

www.irf.com 7

is

IRFR/U4104

Reverse Recovery Current

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

D.U.T

+



-

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

+



V

DD

R

G

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

+

-

Re-Applied Voltage

Inductor Curent

* V

GS

Period

P.W.

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P.W.

Period

VGS=10V

V

DD

I

SD

*

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

R

D.U.T.

D

+

V

DD

-

V

DS

V

GS

R

G

10V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

V

DS

90%

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 18b. Switching Time Waveforms

8 www.irf.com

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

IRFR/U4104

2.38 (.094)

2.19 (.086)

10.42 (.410)

9.40 (.370)

NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIME NSIO N : I NCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIO NS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).

5.46 (.215)

5.21 (.205)

1.02 (.040)

1.64 (.025)

1.52 (. 060)

1.15 (. 045)

1.14 (.045)

2X

0.76 (.030)

2.28 (.090)

6.73 (.265)

6.35 (.250)

- A -

4

1 2 3

1.27 (.050)

0.88 (.035)

6.22 (.245)

5.97 (.235)

- B -

0.89 (.035)

3X

0.64 (.025)

0.25 (.010) M A M B

4.57 (. 180)

D-Pak (TO-252AA) Part Marking Information

Notes: This part m arking information applies to devices produced before 02 /26/2001

EXAMPLE:

THIS IS AN IRFR 120 WITH ASSEMBLY LOT CODE 9U 1P

INTERNATIONAL

RECTIFIER

LOGO

ASS E MBL Y LOT CODE

IRFU120

016

9U 1P

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

0.51 (.020) MIN.

0.58 (. 023)

0.46 (. 018)

LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

DATE CODE YEAR = 0 WEEK = 16

Notes: This part m arking information applies to devices produced aft er 02/26 /2001

EXAMPLE:

THIS IS AN IRFR 120 WITH ASSEMBLY LOT CODE 1234 A SSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE " A"

INTERNATIONAL

RECTIFIER

LOGO

ASS E MBL Y LOT CODE

IRFU120

916A

3412

PA RT NUMBER

DATE CODE YEAR 9 = 1999 WEE K 16 LINE A

www.irf.com 9

IRFR/U4104

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

5.46 (.21 5)

5.21 (.20 5)

1.52 (.060)

1.15 (.045)

- B -

2.28 (.090)

1.91 (.075)

1.14 (.045)

3X

0.76 (.030)

2.28 (.090)

6.73 (.265)

6.35 (.250)

- A -

4

1 2 3

3X

2X

1.27 (.050)

0.88 (.035)

6.22 (.245)

5.97 (.235)

9.65 (.380)

8.89 (.350)

0.89 (.035)

0.64 (.025)

0.25 (.010) M A M B

2.38 (.094)

2.19 (.086)

0.58 (.023)

0.46 (.018)

6.45 (.245)

5.68 (.224)

NOTES: 1 DIMENSIONING & TO L E RA NCING PER ANSI Y 1 4. 5M, 1982. 2 CONTROLLING DIM E NSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).

1.14 (.045)

0.89 (.035)

0.58 (.023)

0.46 (.018)

I-Pak (TO-251AA) Part Marking Information

No t es: This part marking information applies to devices p roduced before 02/26/2001

LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

EXAMPLE:

THIS IS AN IRFR120 WIT H ASS E MBLY LOT CODE 9U1P

INTERNATIONAL

REC TIFIER

LOGO

ASSEMBLY LOT C ODE

IRFU120

016

9U 1P

DATE CODE YEAR = 0 WEEK = 16

Notes: This part marking in formatio n applies to devices produced after 02 /26/2001

EXAMPLE:

THIS IS AN IRFR120 WIT H AS S EMBL Y LOT CODE 5678 ASSE MBLE D ON WW 19, 1999 IN THE ASSEMBLY LI NE " A"

INTERNATIONAL

RECTIF IER

LOGO

ASS E MB LY LOT CODE

IRF U120

56

919A

78

PART NUM BER

DATE CODE YEAR 9 = 1999 WEEK 19 LIN E A

10 www.irf.com

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRR

IRFR/U4104

TRL

12.1 ( .476 )

11.9 ( .469 )

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

FEED DIRECTION

Notes:

Repetitive rating; pulse width limited by



max. junction temperature. (See fig. 11).

 Limited by T

RG = 25Ω, I

, starting TJ = 25°C, L = 0.16mH

Jmax

= 42A, VGS =10V. Part not

AS

recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

16.3 ( .641 )

15.7 ( .619 )

 C

as C  Limited by T

8.1 ( .318 )

7.9 ( .312 )

16 mm

eff. is a fixed capacitance that gives the same charging time

oss

while V

is rising from 0 to 80% V

DS

, see Fig.12a, 12b, 15, 16 for typical repetitive

Jmax

16.3 ( .641 )

15.7 ( .619 )

FEED DIRECTION

DSS

.

avalanche performance.  This value determined from sample failure population. 100% tested to this value in production.  When mounted on 1" square PCB (FR-4 or G-10 Material) .

For recommended footprint and soldering techniques refer to

application note #AN-994

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.7/03

www.irf.com 11

Datasheet IRFR4104, IRFU4104 Datasheet (International Rectifier)

Specifications and Main Features

Frequently Asked Questions

User Manual