Datasheet irfr3504 Datasheet

Page 1
PD - 94499A
AUTOMOTIVE MOSFET
IRFR3504 IRFU3504
Features
● Advanced Process Technology
● Ultra Low On-Resistance
● 175°C Operating Temperature
● Fast Switching
● Repetitive Avalanche Allowed up to Tjmax
Description
Specifically designed for Automotive applications, this HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Addi­tional features of this product are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.
The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.
G
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon limited) 87 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig.9) 61 A ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package limited) 30 I
DM
PD @TC = 25°C Power Dissipation 140 W
V
GS
E
AS
E
(tested) Single Pulse Avalanche Energy Tested Value 480
AS
I
AR
E
AR
T
J
T
STG
Pulsed Drain Current 350
Linear Derating Factor 0.92 W/°C Gate-to-Source Voltage ± 20 V Single Pulse Avalanche Energy 240 mJ
Avalanche Current See Fig.12a, 12b, 15, 16 A Repetitive Avalanche Energy mJ Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
HEXFET® Power MOSFET
D
V
= 40V
DSS
R
S
D-Pak
IRFR3504
DS(on)
I
D
= 9.2mΩ
= 30A
I-Pak
IRFU3504
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
R
θJA
HEXFET(R) is a registered trademark of International Rectifier.
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12/11/02
Page 2
IRFR/U3504
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 870 ––– VGS = 0V, VDS = 0V to 32V
oss
Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.041 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– 7.8 9.2 mΩ VGS = 10V, ID = 30A Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA Forward Transconductance 40 ––– ––– S VDS = 10V, ID = 30A
Drain-to-Source Leakage Current
––– ––– 20
––– ––– 250 VDS = 40V, VGS = 0V, TJ = 125°C Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -200
VDS = 40V, VGS = 0V
µA
nA
VGS = -20V Total Gate Charge ––– 48 71 ID = 30A Gate-to-Source Charge ––– 12 18 nC VDS = 32V Gate-to-Drain ("Miller") Charge ––– 13 20 VGS = 10V Turn-On Delay Time ––– 11 ––– VDD = 20V Rise Time ––– 53 ––– ID = 30A Turn-Off Delay Time ––– 36 ––– RG = 6.8Ω
ns
Fall Time ––– 22 ––– VGS = 10V Internal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
Internal Source Inductance ––– 7.5 ––– from package
and center of die contact Input Capacitance ––– 2150 ––– VGS = 0V Output Capacitance ––– 580 ––– VDS = 25V Reverse Transfer Capacitance ––– 46 ––– pF ƒ = 1.0MHz, See Fig. 5 Output Capacitance ––– 2830 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Output Capacitance ––– 510 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode)
––– –––
––– –––
87
350
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 30A, VGS = 0V Reverse Recovery Time ––– 53 80 ns TJ = 25°C, IF = 30A, VDD = 20V Reverse Recovery Charge ––– 86 130 nC di/dt = 100A/µs  Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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D
S
Page 3
IRFR/U3504
1000
TOP 15V
)
100
A
( t n e
r
r
10
u C e
c
r
1
u o S
­o
t
­n
0.1
i a
r D
,
D
0.01
I
4.0V
BOTTOM 4.0V
20µs PULSE WIDTH
0.001
0.1 1 10 100 1000
Tj = 25°C
VDS, Drain-to-Source Voltage (V)
1000.00
VGS
10V
7.0V
6.0V
5.5V
5.0V
4.5V
1000
TOP 15V
) A
( t
100
n e
r
r u
C e
c
r
10
u o S
­o
t
­n
i a
r
1
D ,
D
I
4.0V
BOTTOM 4.0V
20µs PULSE WIDTH Tj = 175°C
0.1
0.1 1 10 100 1000
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
80
VGS
10V
7.0V
6.0V
5.5V
5.0V
4.5V
)
)
Α
(
t
100.00
n e
r
r u
C e
c
r
10.00
u o S
­o
t
­n
i a
r
1.00
D ,
D
I
TJ = 25°C
V
DS
TJ = 175°C
= 25V
20µs PULSE WIDTH
0.10
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
70
S
( e
c
60
n a
t c u
50
d n o c s
40
n a
r T
30
d
r a
w
r
20
o F ,
s
f
10
G
TJ = 25°C
TJ = 175°C
V
= 25V
DS
20µs PULSE WIDTH
0
0 20 40 60 80 100 120
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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Page 4
IRFR/U3504
100000
10000
) F p
( e c n a
t
i
1000
c a p a
C ,
C
100
10
1 10 100
V
= 0V, f = 1 MHZ
GS
C
= C
iss
rss
oss
= C
= C
gs
gd
ds
C
C
+ Cgd, C
+ C
gd
C
iss
C
oss
C
rss
SHORTED
ds
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100
°
T = 175 C
J
10
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.0 0.5 1.0 1.5 2. 0 2.5 3.0
V ,Source- to-Dr ain Voltage (V)
J
SD
V = 0 V
GS
12
I
=
30A
D
10
8
6
4
GS
2
V , Gate-to-Source Voltage (V)
0
0 10 20 30 40 50
Q , Total Gate Charge (nC)
G
V = 32V
DS
V = 20V
DS
V = 8V
DS
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
) A
( t n e
r
r
100
u C e
c
r u o S
­o
t
­n
10
i a
r D ,
D
I
1
1 10 100 1000
OPERATION IN THIS AREA LIMITED BY RDS(on)
100µsec
1msec
Tc = 25°C Tj = 175°C Single Pulse
10msec
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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Page 5
IRFR/U3504
100
LIMITED BY PACKAGE
80
60
40
D
I , Drain Current (A)
20
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
2.5
87A
I =
D
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Juncti on Temperature ( C)
J
Fig 10. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
thJC
1
D = 0.50
0.20
P
1 2
DM
t
1
t
2
0.10
0.1
0.05
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
t , Rectangular Pulse Duration (sec)
1
Not es:
1. Duty factor D = t / t
2. Peak T = P x Z + T
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRFR/U3504
A
15V
DRIVER
+
-
V
DD
R
20V
V
V
DS
G
GS
L
D.U.T
I
AS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
500
TOP
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting Tj, Junction Temperature ( C)
BOTTO M
°
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
4.0
I
D 12A 21A
30A
) V
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
(
3.5
e g a
t
l o V
d
l
3.0
o h s e
r h
t
2.5
e
t a
G
) h
t
(
2.0
S G
V
1.5
-75 -50 -25 0 25 50 75 100 125 150 175 200
ID = 250µA
TJ , Temperature ( °C )
Fig 14. Threshold Voltage Vs. Temperature
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Page 7
10000
IRFR/U3504
1000
) A
( t n e
100
r
r u
C e
h c
10
n a
l a v A
1
0.1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
0.01
0.05
0.10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆Tj = 25°C due to avalanche losses
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Duty Cycle = Single Pulse
250
TOP Single Pulse BOTTOM 10% Duty Cycle
)
200
J m
( y
g
r e n
150
E e
h c n a
l
100
a v
A ,
R A
50
E
0
25 50 75 100 125 150 175
ID = 30A
Starting TJ , Junction Temperature (°C)
Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T every part type.
. This is validated for
jmax
2. Safe operation in Avalanche is allowed as long asT not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. P
avalanche pulse.
= Average power dissipation per single
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceed
T
(assumed as 25°C in Figure 15, 16).
jmax
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t Z
(D, tav) = Transient thermal resistance, see figure 11)
thJC
av
·f
jmax
is
P
= 1/2 ( 1.3·BV·Iav) = DT/ Z
Fig 16. Maximum Avalanche Energy
Vs. Temperature
D (ave)
I
2DT/ [1.3·BV·Zth]
av =
E
= P
AS (AR)
D (ave)·tav
thJC
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Page 8
IRFR/U3504
+
-
+
-
Reverse Recovery Current
Driver Gate Drive
D.U.T. ISDWaveform
D.U.T. VDSWaveform
D.U.T
+
-
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance Current Transformer
-
+
V
DD
R
G
• dv/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
Re-Applied Voltage
Inductor Curent
* V
GS
Period
P.W.
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
R
D.U.T.
D
V
DD
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
t
d(off)tf
Fig 18b. Switching Time Waveforms
8 www.irf.com
Page 9
D-Pak (TO-252AA) Package Outline
,17(51$7,21$/
/2*
2
5(&7,
),(
5
,5)8
$
/27&2'
(
$66(0%/
<
(;$03
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,7+$66(0%/
<
7+,6,6
$1,5)5
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$
:((.
,17+($66(0%/</
,
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21::
/27&2'
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7180%(
5
Dimensions are shown in millimeters (inches)
IRFR/U3504
5.46 (.215 )
5.21 (.205 )
1.02 (.040)
1.64 (.025)
1.52 (.060)
1.15 (.045)
1.14 (.045)
2X
0.76 (.030)
2.28 (.090)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
1.27 (.050 )
0.88 (.035 )
6.22 (.245)
5.97 (.235)
- B -
0.89 (.035)
3X
0.64 (.025)
0.25 (.010) M A M B
4.57 (.180)
2.38 (.094)
2.19 (.086)
10.42 (.410)
9.40 (.37 0)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14. 5M, 1982.
2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OU TLINE TO- 252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLD ER D IP MAX. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.58 (.02 3)
0.46 (.01 8)
6.45 (.245)
5.68 (.224)
0.51 (.02 0) MIN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS 1 - GAT E
2 - DRAIN 3 - SOURCE
4 - DRAIN
D-Pak (TO-252AA) Part Marking Information
www.irf.com 9
Page 10
IRFR/U3504
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
5.46 (.215)
5.21 (.205)
1.52 (.060)
1.15 (.045)
- B -
2.28 (.090)
1.91 (.075)
1.14 (.045)
3X
0.76 (.030)
2.28 (.090)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
3X
2X
1.27 (.050)
0.88 (.035)
6.22 (.245)
5.97 (.235)
9.65 (.380)
8.89 (.350)
0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.38 (.094)
2.19 (.086)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 C ONFORMS TO J EDEC OUTLINE TO-252AA.
4 D IMENSIONS SHOW N ARE BEF ORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
LEAD ASSIGNMENTS
1 - GATE 2 - DRAIN
3 - SOURCE
4 - DRAIN
10 www.irf.com
Page 11
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
IRFR/U3504
TRL
12.1 ( .476 )
11.9 ( .469 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
 Limited by T
L = 0.52mH, RG = 25Ω, I
, starting TJ = 25°C,
Jmax
AS
= 30A, VGS =10V. Part not recommended for use above this value.
I
≤ 30A, di/dt ≤ 170A/µs, V
SD
DD
≤ V
(BR)DSS
TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
16.3 ( .641 )
15.7 ( .619 )
FEED DIRECTION
C
oss
as C
Limited by T
8.1 ( .318 )
7.9 ( .312 )
16 mm
eff. is a fixed capacitance that gives the same charging time
oss
while V
is rising from 0 to 80% V
DS
, see Fig.12a, 12b, 15, 16 for typical repetitive
Jmax
16.3 ( .641 )
15.7 ( .619 )
FEED DIRECTION
DSS
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
,
When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/02
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