Page 1
PD - 94505
IRFR3410
IRFU3410
HEXFET® Power MOSFET
Applications
l High frequency DC-DC converters
V
DSS
R
DS(on)
max I
100V 39mΩ 31A
D
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective C
to Simplify Design, (See
OSS
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRFR3410
I-Pak
IRFU3410
Absolute Maximum Ratings
Symbol Parameter Max. Units
V
DS
V
GS
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 31
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 22 A
I
DM
PD @TC = 25°C Maximum Power Dissipation 110 W
PD @TA = 25°C Maximum Power Dissipation 3.0
Linear Derating Factor 0.71 mW°C
dv/dt Peak Diode Recovery dv/dt 15 V/ns
T
J
T
STG
Drain-Source Voltage 100 V
Gate-to-Source Voltage ± 20
Pulsed Drain Current 125
Operating Junction and -55 to + 175 °C
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
R
θJA
Junction-to-Case ––– 1.4
Junction-to-Ambient (PCB mount)* ––– 40 °C/W
Junction-to-Ambient ––– 110
Notes through are on page 10
www.irf.com 1
9/23/02
Page 2
IRFR/U3410
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 250 ––– VGS = 0V, VDS = 0V to 80V
oss
Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance ––– 34 39 m Ω VGS = 10V, ID = 18A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 20
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200
VDS = 100V, VGS = 0V
µA
nA
V
= -20V
GS
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 33 ––– ––– S VDS = 25V, ID = 18A
Total Gate Charge ––– 37 56 ID = 18A
Gate-to-Source Charge ––– 10 ––– nC VDS = 50V
Gate-to-Drain ("Miller") Charge ––– 11 ––– VGS = 10V,
Turn-On Delay Time ––– 12 ––– VDD = 50V
Rise Time ––– 27 ––– ID = 18A
Turn-Off Delay Time ––– 40 ––– RG = 9.1Ω
ns
Fall Time ––– 13 ––– VGS = 10V
Input Capacitance ––– 1690 ––– VGS = 0V
Output Capacitance ––– 220 ––– VDS = 25V
Reverse Transfer Capacitance ––– 26 ––– pF ƒ = 1.0MHz
Output Capacitance ––– 1640 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 130 ––– VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Avalanche Characteristics
Parameter Typ. Max. Units
E
AS
I
AR
Single Pulse Avalanche Energy ––– 140 mJ
Avalanche Current ––– 18 A
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
31
125
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 18A, VGS = 0V
Reverse Recovery Time ––– 84 ––– ns TJ = 25°C, IF = 18A
Reverse RecoveryCharge ––– 260 ––– nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2 www.irf.com
D
S
Page 3
IRFR/U3410
1000
V
TOP 15V
D
100
10
10V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
I
GS
8.0V
4.5V
20µs PULSE WIDTH
1
0.1 1 10 100
Tj = 25°C
VDS, Dr ain- to-Source Voltage (V)
1000
)
Α
(
t
n
e
r
r
100
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
D
I
TJ = 175°C
10
1
4.0 5.0 6.0 7.0 8.0 9.0
TJ = 25°C
V
= 50V
DS
20µs PULSE WIDTH
VGS, Gat e-to-Source Voltage (V)
100
V
TOP 15V
D
10
10V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
I
GS
8.0V
4.5V
20µs PULSE WIDTH
1
0.1 1 10 100
Tj = 175°C
VDS, Dr ain- to-Source Voltage (V)
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
e
c
n
a
t
s
i
s
e
R
n
O
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
)
n
o
(
S
D
R
ID = 30A
V
= 10V
GS
2.0
)
d
e
z
i
l
a
m
r
o
N
(
1.0
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Tempera ture ( °C )
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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Page 4
IRFR/U3410
100000
10000
)
F
p
(
e
c
n
a
t
1000
i
c
a
p
a
C
,
C
100
10
1 10 100
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
+ Cgd, C
gs
gd
+ C
ds
Ciss
Coss
Crss
iss
C
rss
C
oss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.0
)
A
(
t
100.0
n
e
r
r
u
C
n
i
a
r
10.0
D
e
s
r
e
v
e
R
,
1.0
D
S
I
0.1
TJ = 175°C
TJ = 25°C
0.0 0.5 1.0 1.5 2.0
VSD, Source-toDrain Voltage (V)
20
SHORTED
ds
gd
)
V
(
e
g
a
t
l
o
V
e
c
r
u
o
S
-
o
t
-
e
t
a
G
,
V
ID= 18A
16
12
8
S
4
G
0
0 102030405060
Q
VDS= 80V
VDS= 50V
VDS= 20V
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
)
A
(
t
100
n
e
r
r
u
C
e
c
r
10
u
o
S
-
o
t
-
n
i
a
r
1
D
,
D
Tc = 25°C
I
V
= 0V
GS
Tj = 175°C
Single Pulse
0.1
1 10 100 1000
V
OPERATION IN THIS AREA
LIMITED BY RDS(on)
, Dr ain- toSource Voltage (V)
DS
100µsec
1msec
10msec
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4 www.irf.com
Page 5
IRFR/U3410
+
-
R
D.U.T.
D
V
DD
32
LIMITED BY PACKAGE
28
24
)
A
(
t
n
20
e
r
r
u
16
C
n
i
a
r
12
D
,
D
I
8
Fig 10a. Switching Time Test Circuit
R
V
DS
V
GS
G
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
0
25 50 75 100 125 150 175
TC , Case Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
10
)
C
1
J
h
t
Z
(
e
s
n
o
p
s
e
R
l
a
m
r
e
h
T
0.1
0.01
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Dur ation (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com 5
Page 6
IRFR/U3410
A
15V
DRIVER
+
V
DD
-
R
V
20V
V
DS
G
GS
L
D.U.T
I
AS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
250
)
J
m
(
y
g
200
r
e
n
E
e
h
c
150
n
a
l
a
v
A
e
100
s
l
u
P
e
l
g
n
i
50
S
,
S
A
E
0
25 50 75 100 125 150 175
I
TOP 7.3A
13A
BOTTOM 18A
Starting TJ, Junction Temper ature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
D
50KΩ
Q
G
V
GS
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
12V
Fig 13b. Gate Charge Test Circuit
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
+
V
-
D
6 www.irf.com
DS
Page 7
IRFR/U3410
+
-
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
• I
controlled by Duty Factor "D"
SD
• D.U.T. - Device Under Test
Period
D =
G
Period
P.W.
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFET® Power MOSFETs
www.irf.com 7
Page 8
IRFR/U3410
TO-251AA (I-Pak) Package Outline
Dimensions are shown in millimeters (inches)
5.46 (.215)
5.21 (.205)
1.52 (.060)
1.15 (.045)
- B -
2.28 (.090)
1.91 (.075)
1.14 (.045)
3X
0.76 (.030)
2.28 (.090)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
3X
2X
1.27 (.050)
0.88 (.035)
6.22 (.245)
5.97 (.235)
9.65 (.380)
8.89 (.350)
0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.38 (.094)
2.19 (.086)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
NOTES:
1 DIMENSIONING & TOLERANCI NG PER ANSI Y1 4. 5M, 1982.
2 CONTROLLING DIME NS I O N : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
TO-251AA (I-Pak) Part Marking Information
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
P
A
T
R
U
N
E
B
R
E
X
A
M
P
E
:
L
I
H
S
T
S
I
A
N
W
T
H
I
A
S
S
T
O
L
O
C
D
A
S
S
E
M
B
L
A
S
E
H
T
N
I
2
0
1
R
F
R
I
E
Y
M
L
B
E
8
5
6
7
E
D
N
O
S
E
L
B
M
W
Y
9
,
1
9
W
L
9
1
9
I
N
E
"
A
"
T
N
E
N
R
I
A
A
L
N
O
T
I
R
E
I
C
E
R
F
T
I
L
G
O
O
A
S
O
L
Y
L
B
S
E
M
T
C
E
D
O
U
1
I
F
0
2
R
1
9
A
9
8
7
6
5
D
Y
W
L
E
I
M
C
A
T
E
D
O
E
A
=
1
9
R
E
E
K
N
E
9
9
9
9
1
A
8 www.irf.com
Page 9
TO-252AA (D-Pak) Package Outline
I
N
T
E
R
N
A
T
I
O
N
A
L
L
O
G
O
R
E
C
T
I
F
I
E
R
3
4
1
2
I
R
F
U
1
2
0
9
1
6
A
L
O
T
C
O
D
E
A
S
S
E
M
B
L
Y
E
X
A
M
P
L
E
:
W
I
T
H
A
S
S
E
M
B
L
Y
T
H
I
S
I
S
A
N
I
R
F
R
1
2
0
Y
E
A
R
9
=
1
9
9
9
D
A
T
E
C
O
D
E
L
I
N
E
A
W
E
E
K
1
6
I
N
T
H
E
A
S
S
E
M
B
L
Y
L
I
N
E
"
A
"
A
S
S
E
M
B
L
E
D
O
N
W
W
1
6
,
1
9
9
9
L
O
T
C
O
D
E
1
2
3
4
P
A
R
T
N
U
M
B
E
R
Dimensions are shown in millimeters (inches)
IRFR/U3410
5.46 (.215)
5.21 (.205)
1.02 (.040)
1.64 (.025)
1.52 (. 060)
1.15 (. 045)
1.14 (.045)
2X
0.76 (.030)
2.28 (.090)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
1.27 (.050)
0.88 (.035)
6.22 (.245)
5.97 (.235)
- B -
0.89 (.035)
3X
0.64 (.025)
0.25 (.010) M A M B
4.57 (. 180)
2.38 (.094)
2.19 (.086)
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIME NSIO N : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIO NS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0.58 (. 023)
0.46 (. 018)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
TO-252AA (D-Pak) Part Marking Information
www.irf.com 9
Page 10
IRFR/U3410
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
FEED DIRECTION
8.1 ( .318 )
7.9 ( .312 )
16 mm
16.3 ( .641 )
15.7 ( .619 )
FEED DIRECTION
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 0.85mH
J
= 18A.
AS
≤ 18A, di/dt ≤ 360A/µs, V
DD
≤ V
(BR)DSS
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
oss
while V
is rising from 0 to 80% V
DS
Calculated continuous current based on maximum allowable
,
junction temperature. Package limitation current is 30A.
TJ ≤ 175°C
* When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
DSS
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.9/02
10 www.irf.com
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