Datasheet irfr18n15d Datasheet

Page 1
SMPS MOSFET
PD- 93815A
IRFR18N15D
IRFU18N15D
HEXFET® Power MOSFET
Applications
V
DSS
R
DS(on)
max I
150V 0.125Ω 18A
Benefits
l Low Gate to Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective C App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
to Simplify Design, (See
OSS
D-Pak
IRFR18N15D
I-Pak
IRFU18N15D
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 18 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 13 A I
DM
PD @TC = 25°C Power Dissipation 110 W
V
GS
dv/dt Peak Diode Recovery dv/dt 3.3 V/ns T
J
T
STG
Pulsed Drain Current 72
Linear Derating Factor 0.71 W/°C Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 175 Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
D
Typical SMPS Topologies
l Telecom 48V input DC-DC Active Clamp Reset Forward Converter
Notes  through are on page 10
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2/23/00
Page 2
IRFR18N15D/IRFU18N15D
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 95 ––– VGS = 0V, VDS = 0V to 120V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Thermal Resistance
R
θJC
R
θJA
R
θJA
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
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Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.17 ––– V/°C Reference to 25°C, ID = 1mA Static Drain-to-Source On-Resistance ––– ––– 0.125 Ω VGS = 10V, ID = 11A Gate Threshold Voltage 3. 0 ––– 5.5 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 120V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 150V, VGS = 0V
µA
nA
VGS = -30V
Parameter Min. Typ. Max. Units Conditions Forward Transconductance 4.2 ––– ––– S VDS = 50V, ID = 11A Total Gate Charge ––– 28 43 ID = 11A Gate-to-Source Charge ––– 7.6 11 nC VDS = 120V Gate-to-Drain ("Miller") Charge ––– 14 21 VGS = 10V, Turn-On Delay Time ––– 8.8 ––– VDD = 75V Rise Time ––– 25 ––– ID = 11A Turn-Off Delay Time ––– 15 ––– RG = 6.8Ω
ns
Fall Time ––– 9. 8 ––– VGS = 10V Input Capacitance ––– 900 ––– VGS = 0V Output Capacitance ––– 190 ––– VDS = 25V Reverse Transfer Capacitance ––– 49 ––– pF ƒ = 1.0MHz Output Capacitance ––– 1160 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Output Capacitance ––– 88 ––– VGS = 0V, VDS = 120V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 200 mJ Avalanche Current ––– 11 A Repetitive Avalanche Energy ––– 11 mJ
Parameter Typ. Max. Units
Junction-to-Case ––– 1.4 Junction-to-Ambient (PCB mount)* ––– 50 °C/W Junction-to-Ambient ––– 110
Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol (Body Diode) Pulsed Source Current integral reverse (Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 11A, VGS = 0V Reverse Recovery Time ––– 130 190 ns TJ = 25°C, IF = 11A Reverse RecoveryCharge ––– 660 980 nC di/dt = 100A/µs Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
18
72
showing the
A
p-n junction diode.
G
D
S
Page 3
IRFR18N15D/IRFU18N15D
100
10
1
D
I , Drain-to-Source Current (A)
0.1
0.1 1 10 100
100
VGS
TOP
15V 10V
9.0V
8.0V
7.5V
7.0V
6.5V
BOTTOM
6.0V
6.0V
20µs PULSE WIDTH T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
100
10
TOP
BOTTOM
VGS 15V 10V
9.0V
8.0V
7.5V
7.0V
6.5V
6.0V
6.0V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 175 C
1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
18A
2.5
°
T = 175 C
J
10
°
T = 25 C
J
D
I , Drain-to-Source Current (A)
V = 50V
DS
1
6 7 8 9 10 11 12
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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Page 4
IRFR18N15D/IRFU18N15D
10000
1000
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
gs gd ds
Ciss
+ Cgd, C
+ C
C C
iss rss oss
gd
SHORTED
ds
20
I =
11A
D
V = 120V
DS
V = 75V
16
12
DS
V = 30V
DS
Coss
100
C, Capacitance(pF)
Crss
10
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
10
°
T = 175 C
J
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.5 0.8 1.1 1.4
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
8
4
GS
V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 10 20 30 40
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
100
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 175 C Single Pulse
1
1 10 100 1000
°
J
V , Drain-to-Source Voltage (V)
DS
BY R
DS(on)
10us
100us
1ms
10ms
13
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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Page 5
20
16
12
8
D
I , Drain Current (A)
4
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Case Temperature
IRFR18N15D/IRFU18N15D
R
D.U.T.
t
d(off)tf
D
+
V
DD
-
V
DS
V
GS
R
G
V
GS
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10% V
GS
t
d(on)tr
Fig 10b. Switching Time Waveforms
10
thJC
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1
SINGLE PULSE
(THERMAL RESPONSE)
t , Rectangular Pulse Duration (sec)
1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRFR18N15D/IRFU18N15D
A
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
Q
GS
Q
GD
DD
500
TOP
400
300
200
100
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
D
4.4A
9.0A 11A
°
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
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Page 7
IRFR18N15D/IRFU18N15D
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
-
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse Recovery Current
Re-Applied Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFET® Power MOSFETs
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Page 8
IRFR18N15D/IRFU18N15D
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
5.46 (.215)
5.21 (.205)
1.02 (.04 0)
1.64 (.02 5)
1.52 (.060)
1.15 (.045)
1.14 (.045)
2X
0.76 (.030)
2.28 (.090)
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
1.27 (.050)
0.88 (.035)
6.22 (.245)
5.97 (.235)
- B -
0.89 (.035 )
3X
0.64 (.025 )
0.25 (.010) M A M B
4.57 (.180)
2.38 (.09 4)
2.19 (.08 6)
10.42 (.410 )
9.40 (.370)
NOTES: 1 DIME N SIONING & T O LER ANCING P ER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 C ON FO RM S TO JED EC O U TLINE TO-2 52AA . 4 DIMENSIONS SHOW N ARE BEFORE SOLDER DIP, SOLD E R D IP M AX. +0.16 (.0 06).
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020) M IN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS 1 - GA TE 2 - D R AIN 3 - S OUR CE 4 - D R AIN
D-Pak (TO-252AA) Part Marking Information
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Page 9
IRFR18N15D/IRFU18N15D
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
5.46 (.215)
5.21 (.205)
1.52 (.060)
1.15 (.045)
- B -
2.28 (.090)
1.91 (.075)
1.14 (.045)
3X
0.76 (.030)
2.28 (.090) 2X
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
1.27 (.050)
0.88 (.035)
6.22 (.245)
5.97 (.235)
9.65 (.380)
8.89 (.350)
0.89 (.035)
3X
0.64 (.025)
0.25 (.01 0 ) M A M B
2.38 (.094)
2.19 (.086)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CO NFO R MS TO JEDE C OUTLIN E TO-252AA. 4 DIM ENSION S SHOW N AR E BEFO RE SOLDE R DIP, S O LD E R DIP MA X. +0.16 (.006).
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
LEAD ASSIGNMEN TS 1 - GATE 2 - DRA IN 3 - SOURCE 4 - DRA IN
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Page 10
IRFR18N15D/IRFU18N15D
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .47 6 )
11.9 ( .46 9 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSION S ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORM S TO EIA-481.
FEED DIRECTION
8.1 ( .318 )
7.9 ( .312 )
16 mm
16.3 ( .641 )
15.7 ( .619 )
FEED DIR ECTION
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature.
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 3.3mH
J
= 11A.
AS
≤ 11A, di/dt ≤ 170A/µs, V
DD
≤ V
(BR)DSS
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
oss
while V
is rising from 0 to 80% V
DS
,
TJ ≤ 175°C
* When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.
DSS
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Data and specifications subject to change without notice. 2/00
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