Datasheet IRFR1018ETRPBF Specification

PD - 97129A

)

IRFR1018EPbF IRFU1018EPbF

Applications

l High Efficiency Synchronous Rectification in

SMPS

l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits

D

G

S

HEXFET® Power MOSFET

V

DSS

R

DS(on

typ.

max. I

D (Silicon Limited

I

D (Package Limited

Benefits

l Improved Gate, Avalanche and Dynamic

dv/dt Ruggedness

l Fully Characterized Capacitance and

Avalanche SOA

l Enhanced body diode dV/dt and dI/dt

Capability

D-Pak

IRFR1018EPbF

GDS

Gate Drain Source

I-Pak

IRFU1018EPbF

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

I

@ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)

D

I

@ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited)

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

d

f

Max.

c

79

c

56

315

110

0.76

± 20

21

-55 to + 175

300

60V

7.1m

8.4m 79A

56A

W/°C

V/ns

: :

c

A

W

V

°C

Avalanche Characteristics

g

e

88

47

11

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

d

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

JA

θ

R

JA

θ

Junction-to-Case

Junction-to-Ambient (PCB Mount)

Junction-to-Ambient

k –––

jk ––– 50

k ––– 110

1.32

°C/W

Notes  through  are on page 2

www.irf.com 1

mJ

A

mJ

4/21/09

IRFR/U1018EPbF

h

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 110 ––– ––– S Q

g

Q

gs

Q

gd

Q

sync

R

G(int)

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 60 ––– ––– V

/ΔT

Breakdown Voltage Temp. Coefficient ––– 0.073 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 7.1 8.4 Gate Threshold Voltage 2.0 ––– 4.0 V Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100

Total Gate Charge ––– 46 69 nC Gate-to-Source Charge ––– 10 ––– Gate-to-Drain ("Miller") Charge ––– 12 ––– Total Gate Charge Sync. (Qg - Qgd)

Internal Gate Resistance

––– 34 –––

–––

0.73 ––– Ω Turn-On Delay Time ––– 13 ––– ns Rise Time ––– 35 ––– Turn-Off Delay Time ––– 55 ––– Fall Time ––– 46 ––– Input Capacitance ––– 2290 ––– Output Capacitance ––– 270 ––– Reverse Transfer Capacitance ––– 130 ––– pF

Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)

––– 390 ––– ––– 630 –––

g

VGS = 0V, ID = 250μA Reference to 25°C, I

= 10V, ID = 47A

V

mΩ

GS

= VGS, ID = 100μA

V

DS

= 60V, VGS = 0V

V

DS

= 48V, VGS = 0V, TJ = 125°C

V

DS

V

= 20V

GS

= -20V

V

GS

VDS = 50V, ID = 47A

= 47A

I

D

= 30V

V

DS

g

= 10V

V

GS

= 47A, VDS =0V, VGS = 10V

I

D

V

= 39V

DD

= 47A

I

D

= 10Ω

R

G

VGS = 10V V

GS

V

DS

g

= 0V = 50V

ƒ = 1.0MHz

= 0V, VDS = 0V to 60V

V

GS

= 0V, VDS = 0V to 60V

V

GS

Conditions

= 5mA

D

g

Conditions

d

i

h

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Calculated continuous current based on maximum allowable junction

temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with

some lead mounting arrangements.

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I

use above this value.

 I

≤ 47A, di/dt ≤ 1668A/μs, V

SD

Continuous Source Current ––– –––

79

c

(Body Diode) Pulsed Source Current ––– ––– 315

(Body Diode)

d

Diode Forward Voltage ––– ––– 1.3 V Reverse Recovery Time ––– 26 39 ns

––– 31 47

Reverse Recovery Charge ––– 24 36 nC

––– 35 53 Reverse Recovery Current ––– 1.8 ––– A Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 Pulse width ≤ 400μs; duty cycle ≤ 2%.  C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

as C

 C

C

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

DS

is rising from 0 to 80% V

DS

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

, starting TJ = 25°C, L = 0.08mH

Jmax

= 47A, VGS =10V. Part not recommended for

AS

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C.

θ

A

MOSFET symbol

showing the integral reverse

p-n junction diode. T

= 25°C, IS = 47A, VGS = 0V

J

TJ = 25°C VR = 51V,

= 125°C IF = 47A

T

J

TJ = 25°C

= 125°C

T

J

TJ = 25°C

is rising from 0 to 80% V

Conditions

.

DSS

.

DSS

G

g

di/dt = 100A/μs

g

2 www.irf.com

D

S

IRFR/U1018EPbF

1000

TOP 15V

) A

( t n e

r

100

u C e

c

r u o S

o

t

n

i

10

a

r D

,

D

I

4.5V

BOTTOM 4.5V

≤60μs PULSE WIDTH

Tj = 25°C

1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

) A

(

t

100

n e

r

r u

C e

c

r u

10

o S

o

t

n

i a

r D

,

D

I

1

TJ = 175°C

TJ = 25°C

V

DS

≤

60μs PULSE WIDTH

= 25V

0.1 2 3 4 5 6 7 8 9

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

) A

( t n e

r

r u

C e

c

r u o S

o

t

n

i a

r D

, I

1000

D

100

10

TOP 15V

BOTTOM 4.5V

VGS

10V

8.0V

6.0V

5.5V

5.0V

4.8V

4.5V

≤60μs PULSE WIDTH

Tj = 175°C

1

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

2.5

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 47A

V

= 10V

GS

2.0

) d e z

i

l a

1.5

m

r o

N

(

1.0

0.5

-60 -40 -20 0 20 40 60 80 100120 140160180

TJ , Junction Temperature (°C)

Fig 4. Normalized On-Resistance vs. Temperature

4000

3000

) F p

( e

c n a

t

i

2000

c a p a

C ,

C

1000

0

V

= 0V, f = 1 MHZ

GS

C

= C

C

iss

rss

oss

= C

C

+ Cgd, C

gs

gd

+ C

ds

iss

oss

rss

SHORTED

ds

gd

1 10 100

VDS, Drain-to-Source Voltage (V)

16

ID= 47A

) V

( e

g

12

a

t

l o V

e c

r u o

8

S

o

t

e

t a

G ,

4

S G

V

VDS= 48V

VDS= 30V

VDS= 12V

0

0 102030405060

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFR/U1018EPbF

1000

) A

( t

100

n e

r

r u

C n

i a

r

10

D e

s

r e v e

R ,

1

D S

I

0.1

TJ = 175°C

TJ = 25°C

V

= 0V

GS

0.0 0.5 1.0 1.5 2.0

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

80

LIMITED BY PACKAGE

60

) A

( t n e

r

r u

C

40

n

i a

r D

,

D

I

20

0

25 50 75 100 125 150 175

TC, Case Temperature (°C)

10000

) A

(

1000

t n e

r

r u

C

100

e c

r u o S

o

t

10

n

i a

r D

,

D

I

LIMITED BY PACKAGE

1

Tc = 25°C Tj = 175°C Single Pulse

0.1

0.1 1 10 100

OPERATION IN THIS AREA LIMITED BY RDS(on)

1msec

10msec

DC

VDS, Drain-toSource Voltage (V)

Fig 8. Maximum Safe Operating Area

) V

(

80

e g a

t

l o V

n w

o d k a e

r B

e c

r u o S

o

t

n

i a

r D ,

S S D

) R B

(

V

Id = 5mA

75

70

65

60

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

100μsec

Fig 9. Maximum Drain Current vs. Case Temperature

0.8

0.6

) J

μ

( y

0.4

g

r e n E

0.2

0.0

0 10 20 30 40 50 60

V

Drain-to-Source Voltage (V)

DS,

Fig 11. Typical C

Stored Energy

OSS

Fig 10. Drain-to-Source Breakdown Voltage

400

) J

m

(

350

y g

r e

300

n E

e h

250

c n a

l a v

200

A e

s

l

150

u P

e

l g

100

n

i S

,

50

S A

E

0

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

I

TOP

5.3A

11A

BOTTOM

47A

D

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

4 www.irf.com

IRFR/U1018EPbF

(

)

τ

10

)

1

C J h

t Z (

e s n o p s e

R l a

m

r e h T

0.001

D = 0.50

0.20

R

0.1

0.01

0.10

0.05

0.02

0.01

SINGLE PULSE ( THERMAL RESPONSE )

τ

J

τ

J

τ

1

τ

Ci= τi/Ri

1

2

R

1

τ

3

R

2

3

τ

2

3

τ

2

3

Notes:

1. Duty Factor D = t1/t2

Ri (°C/W)

4

R

4

0.026741 0.000007

τ

C

0.28078 0.000091

τ

4

τ

4

0.606685 0.000843

0.406128 0.005884

2. Peak Tj = P dm x Zthjc + Tc

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

τι

sec

100

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

) A

(

10

t n e

r

r u

C e

h c n a

l a

1

v A

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤj = 25°C and

0.01

0.05

0.10

Tstart = 150°C.

0.1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

100

TOP Single Pulse

) J

80

m

( y

g

r e n

60

E e

h c n a

l

40

a v

A ,

R A

20

E

0

25 50 75 100 125 150 175

BOTTOM 10% Duty Cycle ID = 47A

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFR/U1018EPbF

4.5

) V

4.0

( e

g a

t

l

3.5

o V

d

l o

3.0

h s e

r h

t

2.5

e

t a

G )

2.0

h

t

(

S G

1.5

V

1.0

-75 -50 -25 0 25 50 75 100 125 150 175

TJ , Temperature ( °C )

ID = 1.0A

ID = 1.0mA

ID = 250μA

ID = 100μA

Fig 16. Threshold Voltage vs. Temperature

14

IF = 47A

12

VR = 51V

TJ = 25°C

10

TJ = 125°C

)

8

A

(

R R

I

6

4

14

IF = 32A

12

VR = 51V

TJ = 25°C

10

TJ = 125°C

)

8

A

(

R R

I

6

4

2

0

0 200 400 600 800 1000

diF /dt (A/μs)

Fig. 17 - Typical Recovery Current vs. dif/dt

320

IF = 32A

280

VR = 51V

TJ = 25°C

240

TJ = 125°C

200

) A

(

160

R R

Q

120

80

2

0

0 200 400 600 800 1000

diF /dt (A/μs)

320

280

240

200

) A

(

160

R R

Q

120

80

40

0

0 200 400 600 800 1000

diF /dt (A/μs)

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

IF = 47A

VR = 51V

TJ = 25°C

TJ = 125°C

0

0 200 400 600 800 1000

diF /dt (A/μs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFR/U1018EPbF

A

D.U.T

+



-



R

G

*

Use P-Channel Driver for P-Channel Measurements

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer

*

• dv/dt controlled by R

• Driver same type as D.U.T.

controlled by Duty Factor "D"

• I

SD

• D.U.T. - Device Under Test



-

+

G

** Reverse Polarity for P-Channel

Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

15V

V

DS

L

DRIVER

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

Reverse Recovery Current

D.U.T. VDSWaveform

V

DD

Re-Applied Voltage

+

**

-

Inductor Curent

*** V

GS

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

t

p

D =

P. W .

Period

V

(BR)DSS

***

VGS=10V

V

DD

I

SD

R

20V

G

V

GS

D.U.T

I

AS

0.01

t

p

Ω

Fig 22a. Unclamped Inductive Test Circuit

R

V

DS

V

GS

R

G

D

D.U.T.

10V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

Fig 23a. Switching Time Test Circuit

0

20K

1K

DUT

+

V

DD

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

+

V

DD

-

10%

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig 23b. Switching Time Waveforms

Id

Vgs

Vds

L

VCC

Vgs(th)

Qgs1

Qgs2QgdQgodr

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

Fig 24b. Gate Charge Waveform

IRFR/U1018EPbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE:

Note: "P" in ass embly line posi tion

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

8 www.irf.com

TH IS IS AN IR FR120 WITH ASSEMBLY LOT CODE 1234 ASS EMBLE D ON WW 16, 2001 IN THE ASSEMBLY LINE "A"

i ndi cates "L ead-F r ee"

"P" in as sembly line position indicates "L ead-F r ee" qu ali fi cati on t o the con s umer -lev el

OR

INTE RNATIONAL

RECTIFIER

LOGO

AS S E MB L Y LOT CODE

INTE RNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

IRF R120

12

IRF R120

116A

PART NUMBER

DATE CODE P = DE S I GNAT E S L E AD- F R E E

34

P = DE S I GNAT E S L E AD- F R E E

YEAR 1 = 2001 WE E K 16 A = ASSEMBLY SITE CODE

PART NUMBER

DATE CODE

3412

YEAR 1 = 2001 WE EK 16 LINE A

PRODU CT (OPTIONAL)

PRODUCT QUALIFIE D TO T HE CONSUMER LEVEL (OPTIONAL)

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

IRFR/U1018EPbF

I-Pak (TO-251AA) Part Marking Information

78

PART NUMBER

DATE CODE YEAR 1 = 2001 WEEK 19 LINE A

EXAMPLE:

TH IS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 ASS EMBLE D ON WW 19, 2001 IN THE ASSEMBLY LINE "A"

Note: "P" in ass embly line position

indicates Lead-Free"

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

IRF U120

56

119A

OR

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY LOT CODE

IRFU120

56 78

PART NUMBER

DATE CODE P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL )

YEAR 1 = 2001 WEEK 19 A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

www.irf.com 9

IRFR/U1018EPbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

FEED DIRECTION

8.1 ( .318 )

7.9 ( .312 )

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

TRR

TRL

16.3 ( .641 )

15.7 ( .619 )

FEED DIRECTION

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Data and specifications subject to change without notice.

This product has been designed for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.4/09

10 www.irf.com