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PD - 93912B
IRFPS3810
HEXFET® Power MOSFET
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
G
D
V
= 100V
DSS
R
S
= 0.009Ω
DS(on)
= 170A
I
D
Description
The HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to
achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed
and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in
a wide variety of applications.
Super-247™
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 170
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 120 A
I
DM
PD @TC = 25°C Power Dissipation 580 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt 2.3 V/ns
T
J
T
STG
Pulsed Drain Current 670
Linear Derating Factor 3.8 W/°C
Gate-to-Source Voltage ± 30 V
Single Pulse Avalanche Energy 1350 mJ
Avalanche Current 100 A
Repetitive Avalanche Energy 58 mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θCS
R
θJA
Junction-to-Case ––– 0.26
Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
Junction-to-Ambient ––– 40
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IRFPS3810
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 2210 ––– VGS = 0V, VDS = 0V to 80V
oss
Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance – –– ––– 0.009 Ω VGS = 10V, ID = 100A
Gate Threshold Voltage 3.0 ––– 5.0 V VDS = 10V, ID = 250µA
Forward Transconductance 52 ––– ––– S VDS = 50V, ID = 100A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 10 0 V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 100V, VGS = 0V
µA
= 30V
GS
nA
VGS = -30V
Total Gate Charge ––– 2 6 0 39 0 ID = 100A
Gate-to-Source Charge ––– 49 74 nC VDS = 80V
Gate-to-Drain ("Miller") Charge ––– 160 250 VGS = 10V
Turn-On Delay Time ––– 24 ––– VDD = 50V
Rise Time ––– 27 0 ––– ID = 100A
Turn-Off Delay Time ––– 45 ––– RG = 1.03Ω
ns
Fall Time ––– 140 ––– VGS = 10V
Internal Drain Inductance
Internal Source Inductance ––– –––
––– –––
5.0
13
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
Input Capacitance ––– 6790 ––– VGS = 0V
Output Capacitance ––– 2470 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 990 ––– ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 10740 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 1180 ––– VGS = 0V, VDS = 80V, ƒ = 1.0MHz
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
170
670
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 100A, VGS = 0V
Reverse Recovery Time ––– 22 0 330 ns TJ = 25°C, IF = 100A
Reverse RecoveryCharge ––– 1640 2460 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 0.27mH
J
= 100A. (See Figure 12)
AS
≤ 100A, di/dt ≤ 350A/µs, V
DD
≤ V
(BR)DSS
Pulse width ≤ 400µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
Calculated continuous current based on maximum allowable
,
junction temperature. Package limitation current is 105A.
oss
while V
is rising from 0 to 80% V
DS
DSS
TJ ≤ 175°C
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D
S
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IRFPS3810
1000
100
10
1
0.1
D
I , Drain-to-Source Current (A)
0.01
0.1 1 10 100
1000
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
5.0V
5.0V
50µs PULSE WIDTH
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
1000
100
10
D
I , Drain-to-Source Current (A)
1
0.1 1 10 100
VGS
TOP
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM
5.0V
5.0V
50µs PULSE WIDTH
T = 175 C
V , Drain-to-Source Voltage (V)
DS
°
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
170A
I =
D
°
T = 175 C
J
100
°
T = 25 C
J
10
D
I , Drain-to-Source Current (A)
V = 50V
DS
1
5 6 7 8 9 10 11 12 13
V , Gate-to-Source Voltage (V)
GS
50µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
10V
GS
°
Vs. Temperature
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IRFPS3810
15000
10000
V
C
C
C
GS
iss
rss
oss
= 0V, f = 1 MHZ
= C
+ Cgd, C
gs
= C
gd
= C
+ C
ds
gd
Ciss
SHORTED
ds
20
I =
D
16
12
100A
V = 80V
DS
V = 50V
DS
V = 20V
DS
5000
C, Capacitance(pF)
0
1 10 100
VDS, Drain-to-Source Voltage (V)
Coss
Crss
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
°
T = 175 C
J
100
°
T = 25 C
J
SD
I , Reverse Drain Current (A)
V = 0 V
10
0.2 0.8 1.4 2.0 2.6
V ,Source-to-Drain Voltage (V)
SD
GS
8
4
GS
V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 100 200 300 400
Q , Total Gate Charge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10000
1000
100
10
, Drain-to-Source Current (A)
D
I
Tc = 25°C
Tj = 175°C
Single Pulse
1
1 10 100 1000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
V
, Drain-toSource Voltage (V)
DS
100µsec
1msec
10msec
13
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
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+
-
200
160
LIMITED BY PACKAGE
IRFPS3810
R
D.U.T.
D
V
DD
V
DS
V
GS
R
G
120
80
D
I , Drain Current (A)
40
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
°
Fig 9. Maximum Drain Current Vs.
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
thJC
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
0.001
0.00001 0.0001 0.001 0.01 0.1
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
P
DM
t
1 2
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFPS3810
A
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
DD
3000
TOP
2500
2000
1500
1000
500
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting T , Junction Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
D
41A
71A
100A
°
Current Regulator
Same Type as D.U.T.
Q
G
12V
Q
GS
V
G
Q
GD
V
GS
Charge
50KΩ
.2µF
.3µF
3mA
Current Sampling Resistors
+
V
D.U.T.
I
G
DS
-
I
D
Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform
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IRFPS3810
+
-
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFET® Power MOSFETs
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IRFPS3810
Super-247™ Package Outline
2X R
3.00 [.118]
2.00 [.079]
20.80 [.818]
19.80 [.780]
C
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
16.10 [.632]
15.10 [.595]
12
A
3
4.25 [.167]
3.85 [.152]
1.60 [.062]
3X
1.45 [.058]
0.25 [.010] B A
5.50 [.216]
4.50 [.178]
1.30 [.051]
3X
1.10 [.044]
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. DIMENSIONS ARE S HOWN IN MILL IMETERS [INCHES]
3. CONTROLLING DIMENS ION: MIL LI MET ER
4. OUT LINE CONFORMS TO JEDEC OUTLINE T O-274AA
0.13 [.005]
2.15 [.084]
1.45 [.058]
4
B
2.35 [.092]
1.65 [.065]
Ø 1.60 [.063]
SECTION E -E
16.10 [.633]
15.50 [.611]
MAX.
0.25 [.010]
13.90 [.547]
13.30 [.524]
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
BA
4
EE
LEAD AS S IGNMENT S
MOSF E T
1.30 [.051]
0.70 [.028]
IGBT
1 - GATE
2 - COLLECTOR
3 - EMITTER
4 - COLLECTOR
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/02
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