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PD- 95142
Document Number: 91258
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IRFPS37N50APbF
SMPS MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High Speed Power Switching
l Lead-Free
V
DSS
500V 0.13Ω 36A
HEXFET® Power MOSFET
R
DS(on)
max I
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN
SUPER-247
1001)
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 36
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 23 A
I
DM
PD @TC = 25°C Power Dissipation 446 W
V
GS
dv/dt Peak Diode Recovery dv/dt 3.5 V/ns
T
J
T
STG
Pulsed Drain Current 144
Linear Derating Factor 3.6 W/°C
Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
D
°C
Typical SMPS Topologies
l Full Bridge Converters
l Power Factor Correction Boost
Notes through are on page 8
09/14/04
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IRFPS37N50APbF
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Document Number: 91258
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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 400 ––– VGS = 0V, VDS = 0V to 400V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Thermal Resistance
R
θJC
R
θCS
R
θJA
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Drain-to-Source Breakdown Voltage 500 ––– ––– V VGS = 0V, ID = 250µA
Static Drain-to-Source On-Resistance ––– ––– 0.13 Ω VGS = 10V, ID = 22A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 400V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 V
Gate-to-Source Reverse Leakage ––– ––– -100
µA
nA
V
= 500V, VGS = 0V
DS
= 30V
GS
V
= -30V
GS
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 20 ––– ––– S VDS = 50V, ID = 22A
Total Gate Charge ––– ––– 180 ID = 36A
Gate-to-Source Charge ––– ––– 46 nC VDS = 400V
Gate-to-Drain ("Miller") Charge ––– ––– 71 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 23 –– – VDD = 250V
Rise Time ––– 98 – –– ID = 36A
Turn-Off Delay Time ––– 52 – –– RG = 2.15Ω
ns
Fall Time ––– 80 ––– RD = 7.0Ω,See Fig. 10
Input Capacitance ––– 5579 ––– VGS = 0V
Output Capacitance ––– 810 ––– VDS = 25V
Reverse Transfer Capacitance ––– 36 ––– pF ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 7905 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 221 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 1260 mJ
Avalanche Current ––– 36 A
Repetitive Avalanche Energy ––– 44 mJ
Parameter Typ. Max. Units
Junction-to-Case ––– 0.28
Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
Junction-to-Ambient ––– 40
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 36A, VGS = 0V
Reverse Recovery Time ––– 570 860 ns TJ = 25°C, IF = 36A
Reverse RecoveryCharge ––– 8.6 13 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
36
144
showing the
A
p-n junction diode.
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IRFPS37N50APbF
Document Number: 91258
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1000
100
10
1
D
I , Drain-to-Source Current (A)
0.1
0.1 1 10 100
1000
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH
T = 25 C
J
V , Drain-to-Source Voltage (V)
DS
°
100
10
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
T = 150 C
°
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
36A
100
°
T = 150 C
J
°
T = 25 C
10
D
I , Drain-to-Source Current (A)
1
4.0 5.0 6.0 7.0 8.0 9.0
V , Gate-to-Source Voltage (V)
GS
J
V = 50V
DS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
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IRFPS37N50APbF
0
A
Document Number: 91258
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100000
10000
1000
V = 0V, f = 1MHz
GS
C = C + C , C SHORTED
iss gs gd ds
C = C
rss gd
C = C + C
oss ds gd
C
iss
C
oss
C, Capacitance (pF)
100
C
rss
10
1 10 100 1000
V , Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
20
I =
36A
D
V = 400V
DS
V = 250V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
DS
V = 100V
DS
FOR TEST CIRCUIT
0
0 40 80 120 160 200
Q , Total Gate C harge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
100
°
T = 150 C
J
10
°
T = 25 C
J
1
SD
I , Reverse Drain Current (A)
V = 0 V
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4
V ,Source-to-Drain Voltage (V)
SD
GS
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
1
10 100 1000 1000
°
J
V , Drain-to-Source Voltage (V)
DS
10us
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
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IRFPS37N50APbF
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1
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Document Number: 91258
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R
D.U.T.
D
V
DD
40
30
V
DS
V
GS
R
G
10V
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D
I , Drain Current (A)
10
Fig 10a. Switching Time Test Circuit
DS
0%
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
0%
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
thJC
D = 0.50
0.1
0.20
0.10
0.05
0.01
Thermal Response (Z )
0.001
0.02
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty fa c to r D = t / t
2. Peak T =P x Z + T
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRFPS37N50APbF
V
S
Current Regulator
I
A
A
Document Number: 91258
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15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
Ω
0.01
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
DD
3000
TOP
2500
2000
1500
1000
500
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Juncti on Temperature ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
580
I
16A
23A
36A
°
D
G
Charge
Fig 13a. Basic Gate Charge Waveform
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
D
-
I
D
Fig 13b. Gate Charge Test Circuit
560
540
520
DSav
V , Avalanche Voltage (V)
500
0 10203040
I , Avalanche Current (A)
av
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRFPS37N50APbF
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+
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Document Number: 91258
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Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
V
DD
VGS=10V
*
Reverse
Recovery
Current
e-Applied
oltage
D.U.T. ISDWaveform
Body Diode Forward
Current
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
di/dt
Diode Recovery
dv/dt
V
I
Fig 14. For N-channel HEXFET® Power MOSFETs
DD
SD
Page 8
IRFPS37N50APbF
Document Number: 91258
www.vishay.com
8
Case Outline and Dimensions — Super-247
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
SD
TJ ≤ 150°C
= 25°C, L = 1.94mH
J
= 36A. (See Figure 12)
AS
≤ 36A, di/dt ≤ 145A/µs, V
DD
≤ V
(BR)DSS
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
,
oss
while V
is rising from 0 to 80% V
DS
DSS
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IRFPS37N50APbF
Document Number: 91258
www.vishay.com
9
Super-247 (TO-274AA) Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
PART NUMBER
INTERNATIONAL RECTIFIER
LOGO
IRFPS37N50A
17
719C
89
ASSEMBLY LOT CODE
Note: "P" in assembly line position
TOP
indi cates "Lead -Free"
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
Data and specifications subject to change without notice.
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
09/04
Page 10
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
International Rectifier
are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN
®
Document Number: 99901 www.vishay.com
Revision: 12-Mar-07 1
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