Page 1
Trr
Absolute Maximum Ratings
ID @ TC = 25°C
Continuous Drain Current, V
@ 10V
ID @ TC = 100°C
Continuous Drain Current, V
@ 10V
I
PD @TC = 25°C
V
T
T
Diode Characteristics
Units
TJ = 125°C, di/dt = 100A/µs
f
TJ = 125°C, di/dt = 100A/µs
f
I
)
PD- 95140
Document Number: 91257
www.vishay.com
1
IRFPS35N50LPbF
SMPS MOSFET
Applications
• Zero Voltage Switching SMPS
V
DSSRDS(on)
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
500V
• Motor Control applications
• Lead-Free
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise immunity
Parameter Max. Units
GS
GS
DM
GS
dv/dt Peak Diode Recovery dv/dt
J
STG
Pulsed Drain Current
Power Dissipation 450 W
Linear Derating Factor 3.6 W/°C
Gate-to-Source Voltage ±30 V
Operating Junction and -55 to + 150
Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw 1.1(10) N•m (lbf•in)
c
e
HEXFET® Power MOSFET
0.125
34
22 A
140
15 V/ns
typ.
typ.
Ω 170ns 34A
.
Super-247™
I
D
Symbol Parameter Min. Typ. Max.
I
S
I
SM
V
SD
t
rr
Q
rr
RRM
t
on
Conditions
Continuous Source Current ––– ––– 34 MOSFET symbol
(Body Diode) A s howing the
Pulsed Source Current ––– ––– 140 integral reverse
(Body Diode)
Diode Forward Voltage ––– ––– 1.5 V
Reverse Recovery Time ––– 170 250 ns
Reverse Recovery Charge ––– 670 1010 nC
Reverse Recovery Current ––– 8.5 ––– A
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD
c
––– 220 330
––– 1500 2200
p-n junction diode.
= 25°C, IS = 34A, VGS = 0V
T
J
= 25°C, IF = 34A
T
J
= 25°C, IS = 34A, VGS = 0V
T
J
= 25°C
T
J
f
f
09/14/04
Page 2
IRFPS35N50LPbF
V
V
/∆T
R
V
I
I
R
Q
Q
Q
t
t
t
t
C
C
C
C
VGS = 0V, V
= 1.0V, ƒ = 1.0 M H z
C
VGS = 0V, V
= 400V, ƒ = 1.0 M H z
C
eff.
C
eff. (ER )
EASSingle Pulse Avalanche Energy
d
IARAvalanche Current
c
EARRepetitive Avalanche Energy
c
R
Junction-to-Case
h
R
R
Junction-to-Ambient
h
Document Number: 91257
www.vishay.com
2
Static @ TJ = 25°C ( u n less otherw ise specif ied )
Symbol Parameter Min. Typ. Max. Units
(BR)DSS
∆
DS(on)
GS(th)
DSS
GSS
G
(BR)DSS
Drain-to-Source Breakdown Voltage 500 ––– ––– V
Breakd ow n Vo lt ag e Tem p . C oe ff icie nt ––– 0. 12 ––– V/°C
J
Static Drain-to-Source On-Resistance ––– 0.125 0.145
Gate Threshold Voltage 3.0 ––– 5.0 V
Drain-to-Source Leakage Current ––– ––– 50 µA
––– ––– 2.0 mA
Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
Interna l Ga te Re sis t anc e ––– 1. 1 ––– Ω
VGS = 0V, ID = 250µA
Reference to 25°C, I
V
Ω
GS
V
DS
V
DS
V
DS
VGS = 30V
V
GS
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 18 ––– ––– S
g
gs
gd
d(on)
r
d(off)
f
iss
oss
rss
oss
oss
oss
oss
Total G ate Charg e ––– – –– 230
Gate-to-Source Charge ––– ––– 65 nC
Gate-t o-D rain ( "M il ler") C ha rge ––– – –– 110
Turn-On Delay Time ––– 24 –––
Rise Time ––– 100 ––– ns
Turn-Off Delay Time ––– 42 –––
Fall Time –––42–––
Input Capacitance ––– 5580 –––
Output Capacitance ––– 590 –––
Reverse Transfer Capacitance ––– 58 ––– pF
Output Capacitance ––– 7290 –––
Output Capacitance ––– 160 –––
Effective Output Capacitance ––– 320 –––
Effective Output Capacitance ––– 220 –––
(Energy Related)
VDS = 50V, ID = 20A
I
= 34A
D
V
DS
V
GS
VDD = 250V
I
= 34A
D
R
G
V
GS
VGS = 0V
V
DS
ƒ = 1.0MHz , See F ig. 5
V
GS
Avalanch e C h a r act er istics
Symbol
Parameter Typ. Units
––– mJ
––– A
––– mJ
Thermal R es i st an ce
Symbol Parameter Typ. Units
JC
θ
CS
θ
JA
θ
Case-to-Sink, Flat, Greased Surface 0.24 °C/W
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting T
I
AS
I
SD
TJ ≤ 150°C.
= 25°C, L = 0.97mH, RG =25Ω,
J
= 34A (See Figure 13)
≤ 34A, di/dt ≤ 765A/µs, V
DD
≤ V
(BR)DSS
Pulse width ≤ 400µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
,
R
while V
oss
C
eff.(ER) is a fixed capacitance that stores the same energy
oss
as C
while VDS is rising from 0 to 80% V
oss
is measured at TJ approximately 90°C
θ
–––
–––
is rising from 0 to 80% V
DS
Conditions
= 1mA
D
= 10V, ID = 20A
f
= VGS, ID = 250µA
= 500V, VGS = 0V
= 400V, VGS = 0V, TJ = 125°C
= -30V
Conditions
= 400V
= 10V, See Fig. 7 & 15
= 1.2Ω
= 10V, See Fig. 10a & 10b
= 25V
DS
DS
= 0V,VDS = 0V to 400V
Max.
560
34
45
Max.
0.28
–––
40
DSS.
.
DSS
f
f
g
Page 3
IRFPS35N50LPbF
Document Number: 91257
www.vishay.com
3
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
I
D
1000
100
10
1
0.1
0.01
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
20µs PULSE WIDTH
0.001
0.1 1 10 100
Tj = 25°C
VDS, Drain-to-Source Voltage (V )
1000
1000
100
10
1
D
I , Drain-to-Source Current (A)
0.1
0.1 1 10 100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH
T = 150 C
J
V , Drain-to-Source Voltage (V)
DS
°
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
34A
100
°
T = 150 C
J
10
1
°
T = 25 C
0.1
D
I , Drain-to-Source Current (A)
0.01
4.0 5.0 6.0 7.0 8.0 9.0 10.0
J
V = 50V
DS
20µs PULSE WIDTH
V , Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
Vs. Temperature
V =
GS
°
10V
Page 4
IRFPS35N50LPbF
Document Number: 91257
www.vishay.com
4
100000
10000
)
F
p
(
e
c
n
a
t
i
1000
c
a
p
a
C
,
C
100
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
gd
C
= C
ds
+ C
oss
Ciss
Coss
+ Cgd, C
gd
Crss
10
1 10 100 1000
VDS, Drain-to-Source Voltage (V )
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
20
I =
34A
D
V = 400V
DS
V = 250V
16
12
DS
V = 100V
DS
SHORTED
ds
30
25
20
)
J
µ
(
y
15
g
r
e
n
E
10
5
0
0 100 200 300 400 500 600
V
Drain-to-Source Voltage (V)
DS,
Fig 6. Typ. Output Capacitance
1000
100
10
Stored Energy vs. V
°
T = 150 C
J
DS
8
4
GS
V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 40 80 120 160 200 240
Q , Total Gate C harge (nC)
G
SEE FIGURE
Fig 7. Typical Gate Charge Vs.
Gate-to-Source Voltage
13
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
Fig 8. Typical Source-Drain Diode
Forward Voltage
Page 5
IRFPS35N50LPbF
V
9
1
V
+
-
Document Number: 91257
www.vishay.com
5
R
D.U.T.
D
V
DD
35
30
25
20
15
V
DS
V
GS
R
G
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D
10
I , Drain Current (A)
5
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 10a. Switching Time Test Circuit
DS
0%
0%
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
thJC
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty fa c to r D = t / t
2. Peak T =P x Z + T
0.001
0.00001 0.0001 0.001 0.01 0.1
t , Rectangular Pulse Duration (sec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Page 6
IRFPS35N50LPbF
I
A
V
S
Current Regulator
0
Document Number: 91257
www.vishay.com
6
1000
OPERATION IN THIS AREA LIMITED
100
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
1
1 10 100 1000 1000
°
J
V , Drain-to-Source Voltage (V)
DS
BY R
DS(on)
10us
100us
1ms
10ms
Fig 12. Maximum Safe Operating Area
15V
V
DS
L
DRIVER
1200
TOP
1000
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Juncti on Tempera t ur e ( C)
J
BOTTOM
Fig 13. Maximum Avalanche Energy
Vs. Drain Current
V
(BR)DSS
t
p
I
15A
22A
34A
°
D
R
G
20V
D.U.T
I
AS
Ω
0.01
t
p
+
V
-
Fig 14a. Unclamped Inductive Test Circuit
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
I
G
Current Sampling Resistors
+
V
D
-
D
Fig 15a. Gate Charge Test Circuit
DD
AS
Fig 14b. Unclamped Inductive Waveforms
Q
G
V
GS
Q
GS
Q
GD
G
Charge
Fig 15b. Basic Gate Charge Waveform
Page 7
IRFPS35N50LPbF
R
V
+
-
Document Number: 91257
www.vishay.com
7
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
V
DD
VGS=10V
*
Reverse
Recovery
Current
e-Applied
oltage
D.U.T. ISDWaveform
Body Diode Forward
Current
dv/dt
di/dt
V
DD
I
SD
D.U.T. VDSWaveform
Body Diode Forward Drop
Inductor Curent
Ripple ≤ 5%
* V
= 5V for Logic Level Devices
GS
Diode Recovery
Fig 14. For N-Channel HEXFET® Power MOSFETs
Page 8
IRFPS35N50LPbF
Document Number: 91257
www.vishay.com
8
Case Outline and Dimensions — Super-247
Super-247 (TO-274AA) Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
Note: "P" in assembl y lin e po sitio n
ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTERNATIONAL RECTIFIER
LOGO
ASSEMBLY LOT CODE
indica tes "Lead-Free"
IRFPS37N50A
17
TOP
PART NUMBER
719C
89
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
Super TO-247™ package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
09/04
Page 9
Legal Disclaimer Notice
Vishay
Notice
The products described herein were acquired by Vishay Intertechnology, Inc., as part of its acquisition of
International Rectifier’s Power Control Systems (PCS) business, which closed in April 2007. Specifications of the
products displayed herein are pending review by Vishay and are subject to the terms and conditions shown below.
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or
anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
International Rectifier
are registered trademarks of International Rectifier Corporation in the U.S. and other countries. All other product
names noted herein may be trademarks of their respective owners.
®
, IR®, the IR logo, HEXFET®, HEXSense®, HEXDIP®, DOL®, INTERO®, and POWIRTRAIN
®
Document Number: 99901 www.vishay.com
Revision: 12-Mar-07 1
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