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PD- 94227
IRFPS35N50L
SMPS MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l ZVS and High Frequency Circuit
l PWM Inverters
V
DSS
500V 0.125Ω 34A
Benefits
l Low Gate Charge Qg results in Simple Drive Requirement
l Improved Gate, Avalanche and Dynamicdv/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche Voltage
and Current
l Low Trr and Soft Diode Recovery
l High Performance Optimised Anti-parallel Diode
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 34
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 22 A
I
DM
PD @TC = 25°C Power Dissipation 450 W
V
GS
T
J
T
STG
Pulsed Drain Current 140
Linear Derating Factor 3.6 W/°C
Gate-to-Source Voltage ± 30 V
dv/dtPeak Diode Recovery dv/dt 11 V/ns
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case )
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
t
rr
Q
I
RRM
t
on
SD
rr
Continuous Source Current ––– ––– 34 MOSFET symbol
(Body Diode) showing the
Pulsed Source Current ––– ––– 140 integral reverse
(Body Diode) p-n junction diode.
Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 34A, VGS = 0V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current ––– 8.5 ––– A
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
––– 170 250 TJ = 25°C IF = 34A
––– 220 330 TJ = 125°C di/dt = 100A/µs
––– 670 1010 nC TJ = 25°C
––– 1.5 2.2 µCTJ = 125°C
Typical SMPS Topologies
l Bridge Converters l All Zero Voltage Switching
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HEXFET® Power MOSFET
ns
R
DS(on)
A
typ. I
Super-247™
G
°C
D
D
S
5/15/02
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IRFPS35N50L
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 320 ––– VGS = 0V, VDS = 0V to 400V
oss
Drain-to-Source Breakdown Voltage 500 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– 0.125 0.145 Ω VGS = 10V, ID = 20A
Gate Threshold Voltage 3.0 –– – 5.0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100
––– ––– 50 µA VDS = 500V, VGS = 0V
––– ––– 2.0 mA VDS = 400V, VGS = 0V, TJ = 125°C
nA
VGS = -30V
Forward Transconductance 18 ––– ––– S VDS = 50V, ID = 20A
Total Gate Charge – –– –– – 230 ID = 34A
Gate-to-Source Charge ––– ––– 65 nC VDS = 400V
Gate-to-Drain ("Miller") Charge ––– ––– 110 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 24 ––– VDD = 250V
Rise Time ––– 100 ––– ID = 34A
Turn-Off Delay Time ––– 42 ––– RG = 1.2Ω
ns
Fall Time ––– 42 ––– VGS = 10V,See Fig. 10
Input Capacitance ––– 5580 ––– VGS = 0V
Output Capacitance ––– 590 ––– VDS = 25V
Reverse Transfer Capacitance ––– 58 ––– pF ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 7290 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 160 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Avalanche Characteristics
Symbol Parameter Typ. Max. Units
E
AS
I
AR
E
AR
Single Pulse Avalanche Energy ––– 560 mJ
Avalanche Current ––– 34 A
Repetitive Avalanche Energy ––– 45 mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R
θJC
R
θCS
R
θJA
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting T
I
= 34A (See Figure 12a)
AS
I
≤ 34A, di/dt ≤ 510A/µs, V
SD
TJ ≤ 150°C.
Junction-to-Case ––– 0.28
Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
Junction-to-Ambient ––– 40
Pulse width ≤ 400µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
= 25°C, L = 0.97mH, RG = 25Ω,
J
≤ V
DD
(BR)DSS
,
oss
as C
oss
while V
is rising from 0 to 80% V
DS
DSS
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Page 3
IRFPS35N50L
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
-
o
t
-
n
i
a
r
D
,
I
D
1000
100
10
1
0.1
0.01
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
20µs PULSE WIDTH
0.001
0.1 1 10 100
Tj = 25°C
VDS, Drain-to-Source Voltage (V)
1000
1000
100
10
1
D
I , Drain-to-Source Current (A)
0.1
0.1 1 10 100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH
T = 150 C
J
V , Drain-to-Source Voltage (V)
DS
°
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
34A
100
°
T = 150 C
J
10
1
°
T = 25 C
0.1
D
I , Drain-to-Source Current (A)
0.01
4.0 5.0 6.0 7.0 8.0 9.0 10.0
J
V = 50V
DS
20µs PULSE WIDTH
V , Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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Page 4
IRFPS35N50L
100000
10000
)
F
p
(
e
c
n
a
t
i
1000
c
a
p
a
C
,
C
100
V
= 0V, f = 1 MHZ
GS
C
= C
iss
gs
C
= C
rss
gd
C
= C
oss
ds
Ciss
Coss
+ Cgd, C
+ C
gd
Crss
10
1 10 100 1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
SHORTED
ds
20
I =
34A
D
V = 400V
DS
V = 250V
16
12
8
4
GS
V , Gate-to-Source Voltage (V)
DS
V = 100V
DS
FOR TEST CIRCUIT
0
0 40 80 120 160 200 240
Q , Total Gate C harge (nC)
G
SEE FIGURE
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
13
100
°
T = 150 C
J
10
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
100
10
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
1
1 10 100 1000 10000
°
J
V , Drain-to-Source Voltage (V)
DS
10us
100us
1ms
10ms
Fig 8. Maximum Safe Operating Area
Forward Voltage
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Page 5
IRFPS35N50L
+
-
R
D.U.T.
D
V
DD
35
30
25
20
15
V
DS
V
GS
R
G
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D
10
I , Drain Current (A)
5
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
thJC
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Thermal Response (Z )
Notes:
1. Duty fa c to r D = t / t
2. Peak T =P x Z + T
0.001
0.00001 0.0001 0.001 0.01 0.1
t , Rectangular Pulse Durati on ( s ec)
1
J DM thJC C
1 2
P
DM
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRFPS35N50L
A
15V
DRIVER
+
-
V
R
G
20V
V
DS
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
DD
1200
TOP
1000
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperat ur e ( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
15A
22A
34A
°
D
Current Regulator
Same Type as D.U.T.
Q
G
12V
Q
GS
V
G
Q
GD
V
GS
Charge
50KΩ
.2µF
.3µF
3mA
Current Sampling Resistors
+
V
D.U.T.
I
G
DS
-
I
D
Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform
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Page 7
IRFPS35N50L
+
-
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
• I
controlled by Duty Factor "D"
SD
• D.U.T. - Device Under Test
Period
D =
G
Period
P.W.
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFET® Power MOSFETs
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Page 8
IRFPS35N50L
Super-247™ Package Outline
2X R
3.00 [.118]
2.00 [.079]
20.80 [.818]
19.80 [.780]
C
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
16.10 [.632]
15.10 [.595]
12
A
3
4.25 [.167]
3.85 [.152]
1.60 [.062]
3X
1.45 [.058]
0.25 [.010] B A
5.50 [.216]
4.50 [.178]
1.30 [.051]
3X
1.10 [.044]
NOTES :
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. DIMENSIONS ARE SHOWN IN MILLIMET E RS [INCHES]
3. CONTR OLL ING DIMENS ION: MIL L IME T E R
4. OU T L INE CONFORMS T O JEDEC OUTLINE TO-274AA
0.13 [.005]
2.15 [.084]
1.45 [.058]
4
B
2.35 [.092]
1.65 [.065]
Ø 1.60 [.063]
SECT ION E-E
16.10 [.633]
15.50 [.611]
MAX.
0.25 [.010]
13.90 [.547]
13.30 [.524]
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
BA
4
EE
LEAD AS S IGNME NT S
MOSF E T
1.30 [.051]
0.70 [.028]
IGBT
1 - GAT E
2 - COLLECT OR
3 - EMITTER
4 - COLLECT OR
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.5/02
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