Datasheet IRFPC60LCPBF Specification

Power MOSFET

TO-247AC

G

D

S

Available

RoHS*

COMPLIANT

IRFPC60LC, SiHFPC60LC

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 600

(Ω)V

R

DS(on)

Q

(Max.) (nC) 120

g

Q

(nC) 29

gs

Q

(nC) 48

gd

Configuration Single

= 10 V 0.40

GS

D

FEATURES

• Ultra Low Gate Charge

• Reduced Gate Drive Requirement

• Enhanced 30 V V

• Reduced C

• Isolated Central Mounting Hole

• Dynamic dV/dt Rated

• Repetitive Avalanche Rated

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

This new series of low charge Power MOSFETs achieve
significantly lower gate charge over conventional MOSFETs.
Utilizing advanced Power MOSFETs technology the device
improvements allow for reduced gate drive requirements,

G

faster switching speeds and increased total system savings.
These device improvements combined with the proven
ruggedness and reliability of Power MOSFETs offer the
designer a new standart in power transistors for switching

S

N-Channel MOSFET

applications.
The TO-247AC package is preferred for
commercial-industrial applications where higher power levels
preclude the use of TO-220AB devices. The TO-247AC is
similar but superior to the earlier TO-218 package because of
its isolated mounting hole.

ORDERING INFORMATION

Package TO-247AC

Lead (Pb)-free

SnPb

IRFPC60LCPbF
SiHFPC60LC-E3
IRFPC60LC
SiHFPC60LC

iss

, C

GS

oss

Rating

, C

rss

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 10

C

DS

± 30

GS

I

D

IDM 64
Linear Derating Factor 2.2 W/°C
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt

b

a

a

= 25 °C P

c

C

Operating Junction and Storage Temperature Range T

E

AS

I

AR

E

AR

D

dV/dt 3.0 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

Mounting Torque 6-32 or M3 screw

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

= 25 V, starting TJ = 25 °C, L = 7.2 mH, Rg = 25 Ω, IAS = 16 A (see fig. 12).

b. V

DD

≤ 16 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.

c. I

SD

d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91244 www.vishay.com
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THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

600

16

1000 mJ

16 A
28 mJ

280 W

- 55 to + 150

d

10 lbf · in

1.1 N · m

www.vishay.com/doc?91000

V

AT

°C

IRFPC60LC, SiHFPC60LC

D

S

G

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thCS

thJC

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Source Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 9.6 A

DS(on)

fs

iss

- 400 -

oss

-39-

rss

g

--29

gs

--

gd

d(on)

r

-43-

d(off)

-38-

f

D

V

V

GS

R

Between lead,
6 mm (0.25") from
package and center of

S

die contact

-40

0.24 -

°C/WCase-to-Sink, Flat, Greased Surface R

-0.45

VGS = 0 V, ID = 250 μA 600 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 20 V - - ± 100 nA

GS

VDS = 600 V, VGS = 0 V - - 25

= 480 V, VGS = 0 V, TJ = 125 °C - - 250

DS

b

- - 0.40 Ω

VDS = 50 V, ID = 9.6 A 11 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

- 3500 -

- - 120

= 16 A, VDS = 360 V,

I

= 10 V

D

see fig. 6 and 13

b

-17-

V

= 300 V, ID = 16 A,

DD

= 4.3 Ω, RD = 18 Ω, see fig. 10

g

b

-57-

-5.0-

-13-

48

μA

pFOutput Capacitance C

nC

ns

nH

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IS = 16 A, VGS = 0 V

TJ = 25 °C, IF = 16 A, dI/dt = 100 A/μs

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

D

G

S

b

--16
A

--64

--1.8V

- 650 980 ns

-6.09.0μC

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

www.vishay.com Document Number: 91244
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THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRFPC60LC, SiHFPC60LC

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 -Typical Output Characteristics, T

= 150 °C

C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91244 www.vishay.com
S11-0443-Rev. B, 14-Mar-11 3

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

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IRFPC60LC, SiHFPC60LC

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

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THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

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Fig. 9 - Maximum Drain Current vs. Case Temperature

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

R

G

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

IRFPC60LC, SiHFPC60LC

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

G

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

t

p

V

DS

V

DD

V

DS

Document Number: 91244 www.vishay.com
S11-0443-Rev. B, 14-Mar-11 5

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 12a - Unclamped Inductive Test Circuit

This datasheet is subject to change without notice.

I

AS

Fig. 12b - Unclamped Inductive Waveforms

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IRFPC60LC, SiHFPC60LC

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

10 V

V

Q

GS

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test

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This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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IRFPC60LC, SiHFPC60LC

Peak Diode Recovery dV/dt Test Circuit

Vishay Siliconix

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

P.W.

Period

+

+

V

DD

-

= 10 Va

V

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91244

.

Document Number: 91244 www.vishay.com
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This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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VERSION 1: FACILITY CODE = 9

Package Information

Vishay Siliconix

TO-247AC (High Voltage)

MILLIMETERS MILLIMETERS

DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES

A 4.83 5.21 D1 16.25 16.85 5

A1 2.29 2.55 D2 0.56 0.76

A2 1.50 2.49 E 15.50 15.87 4

b 1.12 1.33 E1 13.46 14.16 5

b1 1.12 1.28 E2 4.52 5.49 3

b2 1.91 2.39 6 e 5.44 BSC

b3 1.91 2.34 L 14.90 15.40

b4 2.87 3.22 6, 8 L1 3.96 4.16 6

b5 2.87 3.18 Ø P 3.56 3.65 7

c 0.55 0.69 6 Ø P1 7.19 ref.

c1 0.55 0.65 Q 5.31 5.69

D 20.40 20.70 4 S 5.54 5.74

Notes

(1)

Package reference: JEDEC® TO247, variation AC

(2)

All dimensions are in mm

(3)

Slot required, notch may be rounded

(4)

Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body

(5)

Thermal pad contour optional with dimensions D1 and E1

(6)

Lead finish uncontrolled in L1

(7)

Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm

(8)

Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition

Revision: 19-Oct-2020

For technical questions, contact: [email protected]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1

Document Number: 91360

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0.10 AC

M M

E

E/2

(2)

(4)

R/2

B

2 x R

S

D

See view B

2 x e

b4

3 x b

2 x b2

L

C

L1

1

2

3

Q

D

A

A2

A

A

A1

C

Ø k BD

M M

A

ØP

(Datum B)

ØP1

D1

4

E1

0.01 BD

M M

View A - A

Thermal pad

D2

DDE E

C

C

View B

(b1, b3, b5)

Base metal

c1

(b, b2, b4)

Section C - C, D - D, E - E

(c)

Planting

4

3

5

7

4

4

4

Lead Assignments

1. Gate

2. Drain

3. Source

4. Drain

VERSION 2: FACILITY CODE = Y

Package Information

Vishay Siliconix

MILLIMETERS MILLIMETERS

DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES

A 4.58 5.31 D2 0.51 1.30

A1 2.21 2.59 E 15.29 15.87

A2 1.17 2.49 E1 13.72 -

b 0.99 1.40 e 5.46 BSC

b1 0.99 1.35 Ø k 0.254

b2 1.53 2.39 L 14.20 16.25

b3 1.65 2.37 L1 3.71 4.29

b4 2.42 3.43 Ø P 3.51 3.66

b5 2.59 3.38 Ø P1 - 7.39

c 0.38 0.86 Q 5.31 5.69

c1 0.38 0.76 R 4.52 5.49

D 19.71 20.82 S 5.51 BSC

D1 13.08 -

Notes

(1)

Dimensioning and tolerancing per ASME Y14.5M-1994

(2)

Contour of slot optional

(3)

Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body

(4)

Thermal pad contour optional with dimensions D1 and E1

(5)

Lead finish uncontrolled in L1

(6)

Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")

(7)

Outline conforms to JEDEC outline TO-247 with exception of dimension c

Revision: 19-Oct-2020

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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c1

c

b, b2, b4

Plating

Base metal

b1, b3, b5

0.01 M

DB

E1

D1

P

A

P1

D2

K

A2

D

A

A1

C

b2

b

b4

e

L

C

L1

D

S

R

Q

N

R/2

E

B

M

M

DB

M

0.10 MCAM

VERSION 3: FACILITY CODE = N

Package Information

Vishay Siliconix

MILLIMETERS MILLIMETERS

DIM. MIN. MAX. DIM. MIN. MAX.

A 4.65 5.31 D2 0.51 1.35

A1 2.21 2.59 E 15.29 15.87

A2 1.17 1.37 E1 13.46 -

b 0.99 1.40 e 5.46 BSC

b1 0.99 1.35 k 0.254

b2 1.65 2.39 L 14.20 16.10

b3 1.65 2.34 L1 3.71 4.29

b4 2.59 3.43 N 7.62 BSC

b5 2.59 3.38 P 3.56 3.66

c 0.38 0.89 P1 - 7.39

c1 0.38 0.84 Q 5.31 5.69

D 19.71 20.70 R 4.52 5.49

D1 13.08 - S 5.51 BSC

ECN: E20-0545-Rev. F, 19-Oct-2020
DWG: 5971

Notes

(1)

Dimensioning and tolerancing per ASME Y14.5M-1994

(2)

Contour of slot optional

(3)

Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body

(4)

Thermal pad contour optional with dimensions D1 and E1

(5)

Lead finish uncontrolled in L1

(6)

Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")

Revision: 19-Oct-2020

3

Document Number: 91360

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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