Datasheet irfpc60lc-p Datasheet

PD - 99438

HEXFET® Power MOSFET

IRFPC60LC-P

l Ultra Low Gate Charge l Reduced Gate Drive Requirement l Enhanced 30V V l Reduced C l Isolated Central Mounting Hole l Dynamic dv/dt Rated l Repetitive Avalanche Rated

iss

, C

Rating

gs

, C

oss

rss

G

Description

This new series of Surface Mountable Low Charge HEXFET Power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing advanced Hexfet technology the device improvements allow for reduced gate drive requirements, faster switching speeds and increased total system savings. These device improvements combined with the proven ruggedness and reliability of HEXFETs offer the designer a new standard in power transistors for switching applications.

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 16 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 10 A I

DM

PD @TC = 25°C Power Dissipation 280 W

V

GS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt  3.0 V/ns T

J

T

STG

Pulsed Drain Current  64

Linear Derating Factor 2.2 W/°C Gate-to-Source Voltage ±30 V Single Pulse Avalanche Energy  1000 mJ Avalanche Current  16 A Repetitive Avalanche Energy  28 mJ

Operating Junction and -55 to + 150 Storage Temperature Range °C Max Reflow Temperature 225

D

V

= 600V

DSS

R

S

ID = 16A

= 0.40Ω

DS(on)

Surface Mountable

TO-247

Thermal Resistance

Parameter Min. Typ. Max. Units

R

θJC

R

θCS

R

θJA

Junction-to-Case –––– –––– 0.45 Case-to-Sink, Flat, Greased Surface –––– 0.24 –––– °C/W Junction-to-Ambient –––– –––– 40

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04/25/02

IRFPC60LC-P

Electrical Characteristics @ T

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

∆V

(BR)DSS

R

DS(ON)

V

GS(th)

g

fs

I

DSS

I

GSS

Q

g

Q

gs

Q

gd

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

C

iss

C

oss

C

rss

Drain-to-Source Breakdown Voltage 600 ––– ––– VVGS = 0V, ID = 250µA

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.63 ––– V/°C Reference to 25°C, ID = 1mA

J

Static Drain-to-Source On-Resistance ––– ––– 0.40 Ω VGS = 10V, ID = 9.6A  Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA Forward Transconductance 11 ––– ––– SVDS = 50V, ID = 9.6A

Drain-to-Source Leakage Current

Gate-to-Source Forward Leakage ––– ––– 100 V Gate-to-Source Reverse Leakage ––– ––– -100 V Total Gate Charge ––– ––– 120 ID = 16A Gate-to-Source Charge ––– ––– 29 nC VDS = 360V Gate-to-Drain ("Miller") Charge ––– ––– 48 VGS = 10V, See Fig. 6 and 13  Turn-On Delay Time ––– 17 ––– VDD = 300V Rise Time ––– 57 ––– ID = 16A Turn-Off Delay Time ––– 43 ––– RG = 4.3Ω Fall Time ––– 38 ––– RD = 18Ω, See Fig. 10 

Internal Drain Inductance ––– 5.0 –––

Internal Source Inductance ––– 13 –––

Input Capacitance ––– 3500 ––– VGS = 0V Output Capacitance ––– 400 ––– pF VDS = 25V Reverse Transfer Capacitance ––– 39 ––– ƒ = 1.0MHz, See Fig. 5

= 25°C (unless otherwise specified)

J

––– ––– 25 V ––– ––– 250 V

µA

nA

= 600V, VGS = 0V

DS

= 480V, VGS = 0V, TJ = 125°C

DS

= 20V

GS

= -20V

GS

ns

Between lead, 6mm (0.25in.)

nH

from package and center of die contact

D

G

S

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Continuous Source Current MOSFET symbol (Body Diode) showing the Pulsed Source Current integral reverse (Body Diode)  p-n junction diode.

––– ––– 16

––– ––– 64

A

G

Diode Forward Voltage ––– ––– 1.8 V TJ = 25°C, IS = 16A, VGS = 0V  Reverse Recovery Time ––– 650 980 ns TJ = 25°C, IF = 16A Reverse RecoveryCharge ––– 6.0 9.0 µ C di/dt = 100A/µs Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)



Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )

 V

= 25V, starting TJ = 25°C, L = 7.2mH

DD

RG = 25Ω, I

= 16A. (See Figure 12)

AS

 I

≤ 16A, di/dt ≤ 140A/µs, V

SD

DD

≤ V

(BR)DSS

TJ ≤ 150°C

 Pulse width ≤ 300µs; duty cycle ≤ 2%.

,

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D

S

IRFPC60LC-P

)

100

VGS TOP 15V 10V

8.0V

7.0V

6.0V

5.5V

5.0V

10

BOTTOM 4.5V

1

0.1

D

I , Drain-to-Source Current (A)

4.5V

20µs PULSE W IDTH T = 25°C

0.01

0.01 0.1 1 10 100

V , Dra in -to -S ourc e Vo l tage (V

DS

C

Fig 1. Typical Output Characteristics,

TC = 25oC

100

VGS TOP 15V 10V

8.0V

7.0V

6.0V

5.5V

5.0V

10

BOTTOM 4.5V

1

0.1

D

I , Drain-to-Source Current (A)

20µs P U LSE WID TH T = 150°C

0.01

0.01 0.1 1 10 100

V , Dra in -to -S ourc e Vo l tage (V

DS

C

Fig 2. Typical Output Characteristics,

TC = 150oC

3.0

I = 16 A

D

4.5V

T = 150°C

J

10

1

0.1

D

I , D ra in -to -S our ce C urre n t (A )

0.01 45678910

T = 25°C

J

V = 100V

DS

20µs PULSE WIDTH

V , Gate - to -So u rc e Vo lta ge (V )

GS

2.5

2.0

1.5

(N ormalize d )

1.0

0.5

DS(on)

R , Dra in -to -Sou r ce O n R e s is ta n c e

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

T , Junction Temperature (°C

J

V = 1 0V

GS

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature

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IRFPC60LC-P

ge (V)

)

7000

6000

5000

4000

3000

C, Capacitance (pF)

2000

1000

0

110100

V = 0 V , f = 1M Hz

GS

C = C + C , C SHO R T ED

iss gs gd ds

C = C

rss gd

C = C + C

oss ds gd

C

iss

C

oss

C

rss

V , Drain-to-Source Volta

DS

V , Gate-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

100

1000

20

I = 16 A

D

16

12

8

4

GS

V = 360V

DS

V = 240V

DS

V = 120V

DS

FOR TEST CIRCUIT

0

0306090120

Q , Total G ate Ch arge (nC

G

SE E F IGU RE 13

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

OPER ATION IN THIS AREA LIMITED B Y R

DS(on)

100

10

T = 150°C

J

T = 25°C

J

SD

I , R e ve rs e Dra in Cu rre n t (A)

1

0 0.4 0.8 1 .2 1. 6 2

V , Source-to-Drain Voltage (V

SD

Fig 7. Typical Source-Drain Diode

V = 0 V

GS

10

D

I , D ra in Cu rre n t (A)

T = 25°C

C

T = 150 °C

J

Single P u ls e

1

1 10 100 1000 10000

V , Drain-to-Source Voltage (V

DS

Fig 8. Maximum Safe Operating Area

10µs

100µs

1ms

10ms

Forward Voltage

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16

)

IRFPC60LC-P

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

G

12

8

D

4

I , Drain Current (Amps)

0

25 50 75 100 125 150

T , Case Temperature (°C

C

Fig 9. Maximum Drain Current Vs.

Fig 10a. Switching Time Test Circuit

V 90%

10% V

Fig 10b. Switching Time Waveforms

10 V

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

DS

GS

t

d(on)tr

t

d(off)tf

Case Temperature

1

D = 0.5 0

thJC

0.1

0.20

0.10

0.05

P

0.02

0.01

Th e r m a l R e spon s e (Z )

0.001

0.01 SINGLE PULSE

(THERMAL RESPONSE)

0.00001 0.0001 0.001 0.01 0.1 1 10

t , Rectangular Pulse D uration (sec)

1

No te s :

1. D u ty fa cto r D = t / t

2. P e ak T = P x Z + T

DM

J

DM

t

1

t

2

1

th JC

C

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFPC60LC-P

)

D.U.T.

I

AS

L

0.01Ω

+

V

DD

-

R

10 V

V

DS

G

t

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

V

DD

V

DS

I

AS

Fig 12b. Unclamped Inductive Waveforms

2400

2000

1600

1200

800

400

AS

V = 50 V

E , Single Pulse Avalanche Energy (m J)

DD

0

25 50 75 100 125 150

Starting T , Juntion Temperature (°C

J

I T O P 7.2A 10 A BOTTO M 16A

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Current Regulator

Same Type as D.U.T.

D

50KΩ

.2µF

V

GS

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

I

+

V

DS

-

D

10 V

V

Q

G

Q

GS

Q

GD

12V

G

Charge

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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IRFPC60LC-P

Peak Diode Recovery dv/dt Test Circuit

D.U.T

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance Current Transformer

-

+



-



-

+



R

G

Driver Gate Drive

P.W.

• dv/dt controlled by R

• Driver same type as D.U.T.

G

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

Period

D =

Period

P.W.

+

-

VGS=10V

V

DD

*

D.U.T. ISDWaveform

Reverse Recovery Current

Re-Applied Voltage

D.U.T. VDSWaveform

Inductor Curent

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

V

DD

I

SD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS

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IRFPC60LC-P

A

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

- A -

5.50 (.217)

2X

- C -

4.30 (.170)

3.70 (.145)

1.40 (.056)

1.00 (.039)

0.25 (.010)

3.65 (.143)

3.55 (.140)

0.25 (.010)

5.50 (.217)

4.50 (.177)

M

MMB

CA

D

S

20.30 (.800)

19.70 (.775)

14.80 (.583)

14.20 (.559)

2.40 (.094)

2.00 (.079) 2X

5.45 (.215) 2X

15.90 (.626)

15.30 (.602)

- B -

12

3.40 (.133)

3.00 (.118)

3

3X

TO-247AC Part Marking Information

EXAMPLE : THIS IS AN IRFPE30 W ITH ASSEMBLY L O T CO D E 3 A 1 Q

INTE RN A TION AL R E CT IF IE R L O G O

ASSEMBLY LO T C O DE

- D -

2.50 (.089)

1.50 (.059)

3X

2.60 (.102)

2.20 (.087)

IRFPE30

3A1Q 9302

5.30 (.209)

4.70 (.185)

4

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-247-AC .

0.80 (.031)

0.40 (.016)

LEAD ASSIGNMENTS

1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN

PART NUMBER

DATE CODE (Y Y W W ) YY = YEA R WW WEEK

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.04/02

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