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TO-247AC
PD- 91898
SMPS MOSFET
IRFPC50A
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply ( SMPS )
l Uninterruptable Power Supply
l High speed power switching
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss specified ( See AN 1001)
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 11
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 7.0 A
I
DM
PD @TC = 25°C Power Dissipation 180 W
V
GS
dv/dt Peak Diode Recovery dv/dt 4.9 V/ns
T
J
T
STG
Pulsed Drain Current 44
Linear Derating Factor 1.4 W/°C
Gate-to-Source Voltage ± 30 V
Operating Junction and -55 to + 150
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
V
DSS
Rds(on) max I
600V 0.58Ω 11A
SDG
D
°C
Typical SMPS Topology:
l PFC Boost
Notes through are on page 8
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6/23/99
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IRFPC50A
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Dynamic @ TJ = 25°C (unless otherwise specified)
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 81 ––– VGS = 0V, VDS = 0V to 480V
oss
Avalanche Characteristics
E
AS
I
AR
E
AR
Thermal Resistance
R
θJC
R
θCS
R
θJA
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
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Drain-to-Source Breakdown Voltage 600 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient
J
––– 0.65 ––– V/°C Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance ––– ––– 0.58 Ω VGS = 10V, ID = 6.0A
Gate Threshold Voltage 2.0 ––– 4. 0 V VDS = VGS, ID = 250µA
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 480V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100
VDS = 600V, VGS = 0V
µA
nA
VGS = -30V
Parameter Min. Typ. Max. Units Conditions
Forward Transconductance 7.7 ––– ––– S VDS = 50V, ID = 6.0A
Total Gate Charge ––– ––– 70 ID = 11A
Gate-to-Source Charge ––– ––– 19 nC VDS = 480V
Gate-to-Drain ("Miller") Charge ––– ––– 28 VGS = 10V, See Fig. 6 and 13
Turn-On Delay Time ––– 15 ––– VDD = 300V
Rise Time ––– 40 ––– ID = 11A
Turn-Off Delay Time ––– 33 ––– RG = 6.2Ω
ns
Fall Time ––– 29 ––– RD = 30Ω,See Fig. 10
Input Capacitance ––– 2100 ––– VGS = 0V
Output Capacitance ––– 270 ––– VDS = 25V
Reverse Transfer Capacitance ––– 9.7 ––– pF ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 2830 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 74 ––– VGS = 0V, VDS = 480V, ƒ = 1.0MHz
Parameter Typ. Max. Units
Single Pulse Avalanche Energy ––– 920 mJ
Avalanche Current ––– 11 A
Repetitive Avalanche Energy ––– 18 mJ
Parameter Typ. Max. Units
Junction-to-Case ––– 0.65
Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
Junction-to-Ambient ––– 40
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
Diode Forward Voltage ––– ––– 1.4 V TJ = 25°C, IS = 11A, VGS = 0V
Reverse Recovery Time ––– 500 740 ns TJ = 25°C, IF = 11A
Reverse RecoveryCharge ––– 4.0 6 .0 µC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
11
44
showing the
A
p-n junction diode.
G
D
S
Page 3
IRFPC50A
100
10
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 25 C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
100
J
100
10
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
°
T = 150 C
1
1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I =
D
11A
13A
2.5
°
T = 150 C
J
10
°
T = 25 C
J
D
I , Drain-to-Source Current (A)
100V
V = 50V
DS
1
4.0 5.0 6.0 7.0 8.0 9.0
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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Page 4
IRFPC50A
)
,
g
g
g
100000
10000
1000
100
V = 0V, f = 1 M H z
GS
C = C + C
C = C
C = C + C
s gd ds
iss
d
rss
oss ds
C SHORTE D
d
C
iss
C
oss
C, Capacitance (pF)
10
1
1 10 100 1000
V , Drain-to-Source Voltage (V
DS
C
rss
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
20
16
12
GS
V , Gate-to-Source Voltage (V)
11A
I =
13A
D
V = 480V
DS
V = 300V
DS
V = 120V
DS
8
4
FOR TEST CIRCUIT
A
0
0 20 40 60 80
Q , Total Gate Charge (nC)
G
SEE FIGURE
13
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
10
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
°
T = 150 C
J
T = 25 C
J
V ,Source-to-Drain Voltage (V)
SD
°
V = 0 V
GS
Fig 7. Typical Source-Drain Diode
10
D
I , Drain Current (A)I , Drain Current (A)
1
°
= 25 C
C
T T= 150 C
Single Pulse
0.1
10 100 1000 10000
°
J
V , Drain-to-Source Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
10us
100us
1ms
10ms
Forward Voltage
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IRFPC50A
R
D.U.T.
D
+
V
DD
-
12
10
8
V
DS
V
GS
R
G
10V
6
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
D
I , Drain Current (A)
2
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
thJC
Thermal Response (Z )
0.001
0.20
0.1
0.10
0.05
0.02
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
P
DM
1 2
J DM thJC C
t
1
t
2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRFPC50A
A
)
15V
DRIVER
+
-
V
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
DD
2000
TOP
1600
1200
800
400
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
730
720
710
I
D
4.9A
7.0A
11A
°
Charge
700
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
690
680
670
DSav
V , A v alanche Voltage (V)
660
650
012345678910111213
I , A vala n ch e Cu rr en t (A
av
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
A
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Page 7
IRFPC50A
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
Driver Gate Drive
P.W.
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P.W.
+
-
VGS=10V
V
DD
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
V
DD
I
SD
Fig 14. For N-Channel HEXFETS
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Page 8
IRFPC50A
A
Package Outline
TO-247AC Outline
Dimensions are shown in millimeters (inches)
- A -
3.65 (.143)
3.55 (.140)
0.25 (.010)
5.50 (.217)
15.90 (.626)
15.30 (.602)
- B -
D
B
MM
- D -
2.50 (.089)
1.50 (.059)
5.30 (.209)
4.70 (.185)
4
20.30 (.800)
19.70 (.775)
14.80 (.583)
14.20 (.559)
2.40 (.094)
2.00 (.079)
2X
5.45 (.215)
2X
123
3.40 (.133)
3.00 (.118)
1.40 (.056)
3X
1.00 (.039)
0.25 (.010)
2X
- C -
4.30 (.170)
3.70 (.145)
Part Marking Information
TO-247AC
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting T
RG = 25Ω, I
I
≤ 11A, di/dt ≤ 126A/µs, V
SD
TJ ≤ 150°C
EXAMPLE : THIS IS AN IRFPE30
W ITH ASSEMBLY
L O T C O D E 3 A1 Q
= 25°C, L = 15mH
J
= 11A. (See Figure 12)
AS
≤ V
DD
(BR)DSS
5.50 (.217)
4.50 (.177)
3X
A
C
M
S
INTE RN ATION AL
R E CTIF IER
L O G O
ASSEMBLY
LO T C O D E
2.60 (.102)
2.20 (.087)
IRFPE30
3A1Q 9302
Pulse width ≤ 300µs; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the same charging time
oss
as C
,
oss
while V
is rising from 0 to 80% V
DS
NOTES:
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC O UTLINE
TO -24 7-AC.
0.80 (.031)
0.40 (.016)
LEAD ASSIGNMENTS
1 - GATE
2 - DRA IN
3 - SOURCE
4 - DRA IN
PART NUMBER
DATE CODE
(YYW W )
YY = YEA R
WW WEEK
DSS
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/ Data and specifications subject to change without notice. 6/99
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