Datasheet IRFP9140 Datasheet (Intersil)

IRFP9140

Data Sheet July 1999

19A, 100V, 0.200 Ohm, P-Channel Power
MOSFET

This is an advanced power MOSFET designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. It is a P-Channel
enhancement mode silicon gate power field effect transistor
designed for applications such as switching regulators,
switchingconvertors,motor drivers, relay drivers, and drivers
for high power bipolar switching transistors requiring high
speed and low gate drive power. These types can be
operated directly from integrated circuits.

Formerly developmental type TA17521.

Ordering Information

PART NUMBER PACKAGE BRAND

IRFP9140 TO-247 IRFP9140

NOTE: When ordering, use the entire part number.

File Number

Features

• 19A, 100V

DS(ON)

= 0.200Ω

•r

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

Symbol

D

G

S

2292.4

Packaging

DRAIN

(FLANGE)

JEDEC STYLE T0-247

SOURCE

DRAIN

GATE

4-57

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

IRFP9140

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

IRFP9140 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DGR

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DS

D
DM
DM

GS

D

-100 V

-100 V

-19

-12

-76 A
±20 V
150 W

A
A

Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W/oC

Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T

as

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

960 mJ

-55 to 150

300
260

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

GS(TH)VDS

Zero Gate Voltage Drain Current I

On-State Drain Current (Note 2)

I

D(ON) VDS > I
Gate to Source Leakage Current I
Drain to Source On Resistance (Note 2) r

DS(ON)VGS

Forward Transconductance (Note 2) g
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge

Q

g(TOT)VGS

(Gate to Source + Gate to Drain)
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Drain Inductance L

Internal Source Inductance L

Junction to Case R
Junction to Ambient R

DSSVGS

DSS

GSS

fs

r

f

gs
gd

ISS
OSS
RSS

D

S

θJC

θJA

= 0V, ID = -250µA, (Figure 10) -100 - - V

= VGS, ID = -250µA -2.0 - -4.0 V
VDS = Rated BV
VDS = 0.8 x Rated BV

D(ON)

, VGS = 0V - - 25 µA

DSS

, VGS = 0V, TJ= 125oC - - 250 µA

DSS

x r

DS(ON) MAX,VGS

= -10V -19 - - A

VGS = ±20V - - ±100 nA

= -10V, ID = -10A, (Figures 8, 9) - 0.14 0.20 Ω
VDS≤ -50V, ID = -10A, (Figure 12) 5.3 7.9 - S
VDD = -50V, ID≈ -19A, RG = 9.1Ω, RL = 2.5Ω,

VGS = -10V, (Figures 17, 18)
MOSFET Switching Times Are Essentially Indepen­dent of Operating Temperature

- 16 20 ns

- 65 100 ns

-4770ns

-2870ns

= -10V, ID = -19A, VDS = 0.8 x Rated BV
I

= -1.5mA (Figures 14, 19, 20)

G(REF)

DSS,

Gate Charge is Essentially Independent of Operating
Temperature

-3755nC

- 8.7 - nC

-22- nC

VGS = 0V, VDS = -25V, f = 1.0MHz, (Figure 11) - 1200 - pF

- 570 - pF

- 160 - pF

MeasuredBetweenContact
Screw on Header That Is
Closer to Source and Gate
Pins and Center of Die

Measured From the Source
Pin, 6mm (0.25in) From
Header and Source Bond­ing Pad

Modified MOSFET
Symbol Showing the In­ternal Device Induc­tances

D

L

D

G

L

S

S

- 5.0 - nH

-13- nH

- - 0.83oC/W

Free Air Operation - - 30

0

C/W

4-58

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I
Pulse Source to Drain Current

(Note 3)

SD

I

SDM

IRFP9140

Modified MOSFET Symbol
Showing the Integral Re­verse P-N Junction
Diode

D

- - -19 A

- - -76 A

G

S

Source to Drain Diode Voltage (Note 2) V
Reverse Recovery Time t
Reverse Recovery Charge Q

TJ = 25oC, ISD = -19A, VGS = 0V, (Figure 13) - - -1.5 V

SD

TJ = 25oC, ISD = -18A, dISD/dt = 100A/µs - 210 - ns

rr

TJ = 25oC, ISD = -18A, dISD/dt = 100A/µs - 2.0 - µC

RR

NOTES:

2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD= 50V, start TJ= 25oC, L = 4.2mH, RG= 25Ω, peak IAS= 19A. See Figures 15, 16.

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

Unless Otherwise Specified

125

20

16

12

8

, DRAIN CURRENT (A)

D

I

4

0

25 50 75 100 125 150

T

, CASE TEMPERATURE(oC)

C

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

1

0.05

0.2

0.1

0.1

0.05

0.02

-2

10

THERMAL IMPEDANCE

-3

10

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t

, RECTANGULAR PULSE DURATION (s)

1

NORMALIZED

θJC,

Z

FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE

4-59

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

θJC

2

1/t2

x R

θJC

NOTES:
DUTY FACTOR: D = t
PEAK TJ= PDM x Z

-2

10

0.1 1 10

+ T

C

IRFP9140

Typical Performance Curves

100

10

OPERATION IN THIS
AREA IS LIMITED
BY r

DS(ON)

1

TC = 25oC

, DRAIN TO SOURCE CURRENT (A)

T

= MAX RATED

J

DS

I

SINGLE PULSE

0.1
1 10 100

VDS, DRAIN VOLTAGE (V)

Unless Otherwise Specified (Continued)

10µs
100µs

1ms

10ms

100ms

DC

30

24

18

12

6

, DRAIN TO SOURCE CURRENT (A)

DS

I

0

0 -10 -20 -30 -40 -50

VGS = -10V

VGS = -8V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

VGS = -7V

VGS = -6V

VGS = -5V

VGS = -4V

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

30

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

24

18

12

6

, DRAIN TO SOURCE CURRENT (A)

DS

I

0

012345

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

VGS = -10V

VGS = -8V

VGS = -7V
VGS = -6V

VGS = -5V

VGS = -4V

2

10

V

≤ -50V

DS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

10

1

, DRAIN TO SOURCE CURRENT (A)

DS

I

0.1
0246810

o

TJ = 150

VGS, DRAIN TO SOURCE VOLTAGE (V)

TJ = 25

o

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

1.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.2

0.9

0.6

DRAIN TO SOURCE

ON RESISTANCE (Ω)

DS(ON),

0.3

r

0

01632486480

ID, DRAIN CURRENT (A)

VGS = -10V

VGS = -20V

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

3.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = -10V

2.4

1.8

1.2

RESISTANCE

0.6

NORMALIZED DRAIN TO SOURCE ON

0

-60 -40 -20 0 20 40 60 80 100 120 140 160
, JUNCTION TEMPERATURE (oC)

T

J

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4-60

IRFP9140

Typical Performance Curves

1.25
ID = 250µA

1.15

1.05

0.95

BREAKDOWN

0.85

NORMALIZED DRAIN TO SOURCE

0.75

-60 -40 -20 0 20 40 60 80 100 120 140 160
T

, JUNCTION TEMPERATURE (oC)

J

Unless Otherwise Specified (Continued)

FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

15

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

≤ -50V

V

DS

12

2500

2000

1500

1000

C, CAPACITANCE (pF)

500

0

110

NEGATIVE VDS, DRAIN TO SOURCE VOLTAGE (V)

C

C

C

ISS

OSS

RSS

VGS = 0V, f = 1MHz
C

= CGS + C

ISS

C

= C

RSS

C

OSS

GD

≈ CDS + C

GD

GD

10

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

-100

TJ = 150oC

2

9

6

, TRANSCONDUCTANCE (S)

fs

3

g

0

0

8

NEGATIVE I

TJ = 25oC

TJ = 150oC

16

, DRAIN CURRENT (A)

D

24

32

40

-10

TJ = 25oC

-1.0

, SOURCE TO DRAIN CURRENT (A)

SD

I

-0.1

-0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8
NEGATIVE VSD, SOURCE TO DRAIN VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20

16

12

8

VOLTAGE (V)

, GATE TO SOURCE

GS

V

4

ID = -19A

VDS = -80V

= -50V

V

DS

= -20V

V

DS

4-61

0

0 1224364860

Q

, TOTAL GATE CHARGE (nC)

g(TOT)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

IRFP9140

Test Circuits and Waveforms

V

DS

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V
V

GS

t

P

AS

L

R

G

-

V

DD

+

DUT

I

AS

0.01Ω

0

V

DD

I

AS

t

P

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

BV

t

AV

DSS

V

DS

t

ON

t

d(ON)

t

R

L

DUT

R

V

GS

G

-

V

DD

+

0

V

DS

V

GS

0

10%

r

10%

90%

50%

PULSE WIDTH

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

-V

DS

D

S

CURRENT

I

D

SAMPLING

(ISOLATED
SUPPLY)

DUT

DUT

+V

DS

0

V

DS

Q

gs

V

DD

Q

gd

Q

g(TOT)

0

I

G(REF)

12V

BATTERY

0

0.2µF

50kΩ

I

G(REF)

CURRENT

REGULATOR

0.3µF

G

IG CURRENT

SAMPLING

RESISTOR RESISTOR

t

d(OFF)

V

GS

t

OFF

50%

90%

90%

t

f

10%

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

4-62

IRFP9140

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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