Datasheet IRFP4668PbF Datasheet

.

PD -97140

IRFP4668PbF

HEXFET® Power MOSFET

Applications

l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits

Benefits

l Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

l Fully Characterized Capacitance and Avalanche

G

D

V

DSS

R

DS(on)

max I

S

D

typ.

SOA

l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free

S

D

G

TO-247AC

GDS

Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V

@ TC = 100°C Continuous Drain Current, VGS @ 10V

I

D

I

DM

@TC = 25°C

P

D

V

GS

dv/dt T

J

T

STG

Pulsed Drain Current

Maximum Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Peak Diode Recovery

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

c

e

Max.

130

92

520

3.5

± 30

57

-55 to + 175

300

10lbxin (1.1Nxm)

200V

8.0m

9.7m

130A

W/°C

:

A

W

V

V/ns

°C

Avalanche Characteristics

f

d

760

See Fig. 14, 15, 22a, 22b,

mJ

A

mJ

E

AS (Thermally limited)

I

AR

E

AR

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

c

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

JC

θ

R

CS

θ

R

JA

θ

Junction-to-Case

Case-to-Sink, Flat Greased Surface

Junction-to-Ambient

j –––

0.24 ––– °C/W

ij ––– 40

0.29

www.irf.com 1

9/8/08

IRFP4668PbF

h

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

ΔV

(BR)DSS

R

DS(on)

V

GS(th)

I

DSS

I

GSS

R

G

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 150 ––– ––– S Q

g

Q

gs

Q

gd

Q

sync

t

d(on)

t

r

t

d(off)

t

f

C

iss

C

oss

C

rss

eff. (ER)

C

oss

eff. (TR)

C

oss

Drain-to-Source Breakdown Voltage 200 ––– ––– V

/ΔT

Breakdown Voltage Temp. Coefficient ––– 0.21 ––– V/°C

J

Static Drain-to-Source On-Resistance ––– 8.0 9.7 Gate Threshold Voltage 3.0 ––– 5.0 V Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100 Internal Gate Resistance ––– 1.0 ––– Ω

Total Gate Charge ––– 161 241 nC Gate-to-Source Charge ––– 54 ––– Gate-to-Drain ("Miller") Charge ––– 52 ––– Total Gate Charge Sync. (Qg - Qgd)

––– 109 ––– Turn-On Delay Time ––– 41 ––– ns Rise Time ––– 105 ––– Turn-Off Delay Time ––– 64 ––– Fall Time ––– 74 ––– Input Capacitance ––– 10720 ––– Output Capacitance ––– 810 ––– Reverse Transfer Capacitance ––– 160 ––– pF

Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)

––– 630 –––

––– 790 –––

g

VGS = 0V, ID = 250μA Reference to 25°C, I

= 10V, ID = 81A

V

mΩ

GS

= VGS, ID = 250μA

V

DS

= 200V, VGS = 0V

V

DS

= 200V, VGS = 0V, TJ = 125°C

V

DS

= 20V

V

GS

= -20V

V

GS

VDS = 50V, ID = 81A

= 81A

I

D

= 100V

V

DS

= 10V

= 130V

= 0V = 50V

f

V

GS

I

= 81A, VDS =0V, VGS = 10V

D

V

DD

= 81A

I

D

= 2.7Ω

R

G

VGS = 10V V

GS

V

DS

ƒ = 1.0MHz

= 0V, VDS = 0V to 160V

V

GS

= 0V, VDS = 0V to 160V

V

GS

Conditions

= 5mA

D

f

Conditions

c

h

g

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

I

RRM

t

on

Notes:

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

RG = 25Ω, I

use above this value.

 I

≤ 81A, di/dt ≤ 520A/μs, V

SD

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

Continuous Source Current ––– –––

130

(Body Diode) Pulsed Source Current ––– ––– 520

(Body Diode)

c

Diode Forward Voltage ––– ––– 1.3 V Reverse Recovery Time ––– 130 ––– ns

––– 155 ––– Reverse Recovery Charge ––– 633 ––– nC

––– 944 ––– Reverse Recovery Current ––– 8.7 ––– A Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

 C

eff. (TR) is a fixed capacitance that gives the same charging time

oss

, starting TJ = 25°C, L = 0.23mH

Jmax

= 81A, VGS =10V. Part not recommended for

AS

as C

 C

C

while V

oss

eff. (ER) is a fixed capacitance that gives the same energy as

oss

while V

oss

DS

is rising from 0 to 80% V

DS

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

mended footprint and soldering techniques refer to application note #AN-994.

 R

is measured at TJ approximately 90°C.

θ

MOSFET symbol

A

showing the integral reverse

p-n junction diode.

= 25°C, IS = 81A, VGS = 0V

T

J

TJ = 25°C VR = 100V,

= 125°C IF = 81A

T

J

TJ = 25°C

= 125°C

T

J

TJ = 25°C

is rising from 0 to 80% V

DSS

Conditions

di/dt = 100A/μs

.

DSS

.

D

G

S

f

2 www.irf.com

IRFP4668PbF

1000

TOP 15V

) A

100

( t n e

r

r u

C

10

e c

r u o S

o

1

t

n

i a

r D

,

D

0.1

I

≤60μs PULSE WIDTH

Tj = 25°C

BOTTOM 4.5V

4.5V

0.01

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000

)

Α

(

t n

100

e

r

r u

C e

c

r u o S

o

t

n

i a

r D

,

D

I

TJ = 175°C

10

TJ = 25°C

1

V

= 50V

DS

≤

60μs PULSE WIDTH

0.1

3.0 4.0 5.0 6.0 7.0 8.0 9.0

VGS, Gate-to-Source Voltage (V)

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

1000

) A

( t n e

r

100

u C e

c

r u o S

o

t

n

i

10

a

r D

,

D

I

4.5V

≤60μs PULSE WIDTH

Tj = 175°C

1

0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

3.5

e c n a

t s

i s e

R n O e

c

r u o S

o

t

n

i a

r D

,

) n o

( S D

R

ID = 81A

V

GS

= 10V

3.0

2.5

) d e

2.0

z

i

l a

m

r

1.5

o N

(

1.0

0.5

0.0

-60 -40 -20 0 20 40 60 80 100120 140160180

TJ , Junction Temperature (°C)

TOP 15V

BOTTOM 4.5V

VGS

10V

8.0V

7.0V

6.0V

5.5V

5.0V

Fig 3. Typical Transfer Characteristics

16000

12000

) F p

( e

c n a

t

i c a p a

C ,

C

8000

4000

0

V

= 0V, f = 1 MHZ

GS

C

= C

C

+ Cgd, C

gs

gd

+ C

ds

iss

oss

rss

ds

gd

C

iss

rss

oss

1 10 100

VDS, Drain-to-Source Voltage (V)

SHORTED

Fig 4. Normalized On-Resistance vs. Temperature

16

ID= 81A

) V

( e

g

12

a

t

l o V

e c

r u o

8

S

o

t

e

t a

G ,

4

S G

V

0

0 40 80 120 160 200

VDS= 160V

VDS= 100V

VDS= 40V

Q

Total Gate Charge (nC)

G

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

www.irf.com 3

IRFP4668PbF

1000

) A

( t

100

n e

r

r u

C n

i a

r

10

D e

s

r e v e

R ,

1

D S

I

0.1

TJ = 175°C

TJ = 25°C

0.0 0.5 1.0 1.5

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode

Forward Voltage

140

120

)

100

A

( t n e

r

80

u C n

i a

60

r D

,

D

40

I

20

0

25 50 75 100 125 150 175

TC , CaseTemperature (°C)

Fig 9. Maximum Drain Current vs.

Case Temperature

14

12

10

) J

μ

8

( y

g

r e

6

n E

4

2

0

0 40 80 120 160 200

V

Drain-to-Source Voltage (V)

DS,

V

GS

= 0V

10000

) A

(

1000

t n e

r

r u

C

100

e c

r u o S

o

t

10

n

i a

r D

,

1

D

I

Tc = 25°C Tj = 175°C Single Pulse

0.1

0.1 1 10 100 1000

OPERATION IN THIS AREA LIMITED BY RDS(on)

100μsec

10msec

1msec

DC

VDS, Drain-toSource Voltage (V)

Fig 8. Maximum Safe Operating Area

) V

(

250

e g a

t

l o V

n w

o d k a e

r B

e c

r u o S

o

t

n

i a

r D ,

S S D

) R B

(

V

Id = 5mA

240

230

220

210

200

190

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

Fig 10. Drain-to-Source Breakdown Voltage

2500

) J

m

( y

g

r

2000

e n E

e h c

1500

n a

l a v A

e s

1000

l u P

e

l g n

i

500

S

, S A

E

0

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

I

TOP

18A

24A

BOTTOM

D

81A

Fig 11. Typical C

Stored Energy

OSS

Fig 12. Maximum Avalanche Energy Vs. DrainCurrent

4 www.irf.com

1

τ

)

C J h

t Z (

e s n o p s e

R l a

m

r e

0.001

h T

0.0001

D = 0.50

0.1

0.20

0.10

R

2

3

R

2

τ

2

τ

2

Ri (°C/W)

R

3

τ

C

0.063359 0.000278

τ

3

τ

3

0.110878 0.005836

0.114838 0.053606

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

τι

0.01

0.05

0.02

0.01

τ

J

τ

J

τ

1

τ

1

Ci= τi/Ri

1

R

1

SINGLE PULSE ( THERMAL RESPONSE )

1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔTj = 150°C and

)

Duty Cycle = Single Pulse

A

(

100

t

n

e

r

u

C

e

h

c

n

a

l

a

10

v

A

0.01

0.05

0.10

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ΔΤj = 25°C and

Tstart = 150°C.

1

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

IRFP4668PbF

(sec)

800

TOP Single Pulse

) J

m

600

( y

g

r e n E

e h

400

c n a

l a v A ,

R

200

A

E

0

25 50 75 100 125 150 175

BOTTOM 1% Duty Cycle ID = 81A

Starting TJ , Junction Temperature (°C)

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T

2. Safe operation in Avalanche is allowed as long asT

. This is validated for every part type.

jmax

is not exceeded.

jmax

3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.

4. P

= Average power dissipation per single avalanche pulse.

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ΔT = Allowable rise in junction temperature, not to exceed T

(assumed as

jmax

25°C in Figure 14, 15). t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t Z

(D, tav) = Transient thermal resistance, see Figures 13)

thJC

P

D (ave)

·f

av

= 1/2 ( 1.3·BV·Iav) = DT/ Z

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

D (ave)·tav

thJC

Fig 15. Maximum Avalanche Energy vs. Temperature

www.irf.com 5

IRFP4668PbF

6.0

) V

(

5.0

e g a

t

l o

4.0

V d

l o h s e

3.0

r h

t e

t a

2.0

G ) h

t

(

S G

1.0

V

0.0

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 1.0A

ID = 1.0mA

ID = 250μA

TJ , Temperature ( °C )

Fig 16. Threshold Voltage Vs. Temperature

70

60

50

) A

40

(

M

R

30

R

I

20

10

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

IF = 81A

VR = 100V

TJ = 125°C

TJ = 25°C

70

60

50

) A

40

(

M

R

30

R

I

20

10

0

100 200 300 400 500 600 700 800 900 1000

IF = 52A

VR = 100V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 17 - Typical Recovery Current vs. dif/dt

5000

4000

)

3000

C n

(

R

2000

Q

IF = 52A

1000

0

100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

VR = 100V

TJ = 125°C

TJ = 25°C

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

5000

4000

)

3000

C n

(

R

2000

Q

IF = 81A

1000

0

100 200 300 400 500 600 700 800 900 1000

VR = 100V

TJ = 125°C

TJ = 25°C

dif / dt - (A / μs)

Fig. 20 - Typical Stored Charge vs. dif/dt

6 www.irf.com

IRFP4668PbF

A





D.U.T

+

-

R

G

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

-

• Low Leakage Inductance Current Transformer



-

• dv/dt controlled by R

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

G

Reverse Recovery

+

-

Current

Re-Applied Voltage

+

V

DD

Driver Gate Drive

P.W.

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Current

Inductor Curent

* V

GS

Period

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

= 5V for Logic Level Devices

D =

P. W .

Period

VGS=10V

V

DD

I

SD

*

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

V

15V

V

DS

L

DRIVER

t

p

(BR)DSS

R

V

20V

G

GS

D.U.T

I

AS

0.01

t

p

Ω

+

V

DD

-

Fig 22a. Unclamped Inductive Test Circuit

R

V

DS

V

GS

R

G

10V

V

GS

Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %

D

D.U.T.

Fig 23a. Switching Time Test Circuit

Current Regulator

Same Type as D.U.T.

50KΩ

.2μF

12V

V

GS

3mA

.3μF

D.U.T.

+

V

DS

-

I

AS

Fig 22b. Unclamped Inductive Waveforms

V

DS

90%

+

V

DD

-

10% V

GS

t

d(on)tr

t

d(off)tf

Fig 23b. Switching Time Waveforms

Vds

Vgs(th)

Id

Vgs

I

G

Current Sampling Resistors

Fig 24a. Gate Charge Test Circuit

www.irf.com 7

I

D

Qgs1

Qgs2 Qgd Qgodr

Fig 24b. Gate Charge Waveform

IRFP4668PbF

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

EXAMPLE:

Note: "P" in ass embly line pos ition

TO-247AC packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

8 www.irf.com

THIS IS AN IR FPE 30 WI T H AS S E MB LY LOT CODE 5657

AS S EMBLE D ON WW 35, 2001 IN THE AS SEMBLY LINE "H"

in dicates "L ead-F ree"

INTER NATIONAL

RECTIF IER

LOGO

AS S E MB L Y LOT CODE

IRFP E30

135H

56 57

PAR T NUMBER

DATE CODE YEAR 1 = 2001 WEEK 35 LINE H

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 09/08